Datasheet

66
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown
in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
T0
).
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable fre-
quency output on the Output Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 69. for details.
The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an
Output Compare interrupt request.
11.2.2 Definitions
Many register and bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare
Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 11-1 are also used extensively throughout the document.
11.3 Timer/Counter0 Prescaler and Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
Clock Select logic which is controlled by the Clock Select (c) bits located in the Timer/Counter0 Control Register
(TCCR0B).
11.3.1 Internal Clock Source with Prescaler
Timer/Counter0 can be clocked directly by the system clock (by setting the CS0[2:0] = 1). This provides the fastest
operation, with a maximum timer/counter clock frequency equal to system clock frequency (f
CLK_I/O
). Alternatively,
one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either
f
CLK_I/O
/8, f
CLK_I/O
/64, f
CLK_I/O
/256, or f
CLK_I/O
/1024.
11.3.2 Prescaler Reset
The prescaler is free running, i.e. it operates independently of the Clock Select logic of Timer/Counter0. Since the
prescaler is not affected by the timer/counter’s clock select, the state of the prescaler will have implications for situ-
ations where a prescaled clock is used. One example of a prescaling artifact is when the timer/counter is enabled
and clocked by the prescaler (6 > CS0[2:0] > 1). The number of system clock cycles from when the timer is
enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor
(8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution.
Table 11-1. Definitions
Constant Description
BOTTOM The counter reaches BOTTOM when it becomes 0x00
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the
value stored in the OCR0A Register. The assignment depends on the mode of operation