Datasheet
38
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately
after waking up.
• Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0
These bits select between the three available sleep modes as shown in Table 7-2.
• Bit 2 – BODSE: BOD Sleep Enable
BOD disable functionality is available in some devices, only. See “Limitations” on page 36.
The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is con-
trolled by a timed sequence.
This bit is unused in devices where software BOD disable has not been implemented and will read as zero in those
devices.
7.5.2 PRR – Power Reduction Register
The Power Reduction Register provides a method to reduce power consumption by allowing peripheral clock sig-
nals to be disabled.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, opera-
tion will continue like before the shutdown.
• Bit 2 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, opera-
tion will continue like before the shutdown.
• Bit 1 – PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI
again, the USI should be re initialized to ensure proper operation.
• Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. Note that the ADC
clock is also used by some parts of the analog comparator, which means that the analogue comparator can not be
used when this bit is high.
Table 7-2. Sleep Mode Select
SM1 SM0 Sleep Mode
00Idle
0 1 ADC Noise Reduction
1 0 Power-down
11Reserved
Bit 76543 210
0x20 – – – – PRTIM1 PRTIM0 PRUSI PRADC PRR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0