Datasheet

31
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
6.3 System Clock Prescaler
The ATtiny25/45/85 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 32.
This feature can be used to decrease power consumption when the requirement for processing power is low. This
can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous
peripherals. clk
I/O
, clk
ADC
, clk
CPU
, and clk
FLASH
are divided by a factor as shown in Table 6-15 on page 33.
6.3.1 Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock
system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous
setting, nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster
than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were
readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock fre-
quency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2
is the period corresponding to the new prescaler setting.
6.4 Clock Output Buffer
The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To enable the output, the
CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on
the system. Note that the clock will not be output during reset and that the normal operation of the I/O pin will be
overridden when the fuse is programmed. Internal RC Oscillator, WDT Oscillator, PLL, and external clock (CLKI)
can be selected when the clock is output on CLKO. Crystal oscillators (XTAL1, XTAL2) can not be used for clock
output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.
6.5 Register Description
6.5.1 OSCCAL – Oscillator Calibration Register
• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process varia-
tions from the oscillator frequency. A pre-programmed calibration value is automatically written to this register
during chip reset, giving the Factory calibrated frequency as specified in Table 21-2 on page 164. The application
software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies
as specified in Table 21-2 on page 164. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected
accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM
or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency
range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other
words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL[6:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest fre-
quency in that range, and a setting of 0x7F gives the highest frequency in the range.
Bit 76543210
0x31 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value