Datasheet

114
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Figure 15-6. Start Condition Detector, Logic Diagram
The start condition detector is working asynchronously and can therefore wake up the processor from power-down
sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this
feature the oscillator start-up time (set by CKSEL fuses, see “Clock Systems and their Distribution” on page 23)
must also be taken into consideration. Refer to the description of the USISIF bit on page 115 for further details.
15.3.6 Clock speed considerations
Maximum frequency for SCL and SCK is f
CK
/ 2. This is also the maximum data transmit and receive rate in both
two- and three-wire mode. In two-wire slave mode the Two-wire Clock Control Unit will hold the SCL low until the
slave is ready to receive more data. This may reduce the actual data rate in two-wire mode.
15.4 Alternative USI Usage
The flexible design of the USI allows it to be used for other tasks when serial communication is not needed. Below
are some examples.
15.4.1 Half-Duplex Asynchronous Data Transfer
Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher perfor-
mance UART than by software, only.
15.4.2 4-Bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked
externally, both clock edges will increment the counter value.
15.4.3 12-Bit Timer/Counter
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.
15.4.4 Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag
and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit.
15.4.5 Software Interrupt
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
SDA
SCL
Write( USISIF)
CLOCK
HOLD
USISIF
DQ
CLR
DQ
CLR