Datasheet

96
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram.
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on
the fast 25.6 MHz PCK clock in the asynchronous mode.
The following Figure 13-3 shows the block diagram for Timer/Counter1.
8-BIT DATABUS
OCR1A OCR1A_SI
TCNT_SO
OCR1C OCR1C_SI
TCCR1 TCCR1_SI
GTCCR GTCCR_SI
TCNT1 TCNT1_SI
OCF1A OCF1A_SI
TOV1 TOV1_SI
TOV1_SO
OCF1A_SO
TCNT1
S
A
S
A
PCKE
CK
PCK
IO-registers Input synchronization
registers
Timer/Counter1 Output synchronization
registers
SYNC
MODE
ASYNC
MODE
1 PCK Delay No Delay~1 CK Delay
1PCK Delay No Delay
TCNT1
OCF1A
TOV1
1..2 PCK Delay
~1 CK Delay1..2 PCK Delay