Datasheet

79
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 11-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation”
on page 71).
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
11.9.3 TCCR0B – Timer/Counter Control Register B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC0A output is changed according to its COM0A[1:0] bits setting. Note that
the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A[1:0] bits that determines
the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC0B output is changed according to its COM0B[1:0] bits setting. Note that
the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B[1:0] bits that determines
the effect of the forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.
Table 11-5. Waveform Generation Mode Bit Description
Mode
WGM
02
WGM
01
WGM
00
Timer/Counter Mode
of Operation TOP
Update of
OCRx at
TOV Flag
Set on
0 0 0 0 Normal 0xFF Immediate MAX
(1)
1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
(2)
2 0 1 0 CTC OCRA Immediate MAX
(1)
3 0 1 1 Fast PWM 0xFF BOTTOM
(2)
MAX
(1)
4 1 0 0 Reserved – – –
5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM
(2)
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA BOTTOM
(2)
TOP
Bit 7 6 5 4 3 2 1 0
0x33 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/Write W W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0