Datasheet

78
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
When OC0A/OC0B is connected to the I/O pin, the function of the COM0A[1:0]/COM0B[1:0] bits depend on the
WGM0[2:0] bit setting. Table 11-2 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to a
normal or CTC mode (non-PWM).
Table 11-3 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 73 for more details.
Table 11-4 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode.
Note: 1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 74 for more
details.
• Bits 3:2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
Table 11-2. Compare Output Mode, non-PWM Mode
COM0A1
COM0B1
COM0A0
COM0B0 Description
0 0 Normal port operation, OC0A/OC0B disconnected.
0 1 Toggle OC0A/OC0B on Compare Match
1 0 Clear OC0A/OC0B on Compare Match
1 1 Set OC0A/OC0B on Compare Match
Table 11-3. Compare Output Mode, Fast PWM Mode
(1)
COM0A1
COM0B1
COM0A0
COM0B0 Description
0 0 Normal port operation, OC0A/OC0B disconnected.
01Reserved
10
Clear OC0A/OC0B on Compare Match, set OC0A/OC0B at BOTTOM
(non-inverting mode)
11
Set OC0A/OC0B on Compare Match, clear OC0A/OC0B at BOTTOM
(inverting mode)
Table 11-4. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0A1
COM0B1
COM0A0
COM0B0 Description
0 0 Normal port operation, OC0A/OC0B disconnected.
01Reserved
10
Clear OC0A/OC0B on Compare Match when up-counting.
Set OC0A/OC0B on Compare Match when down-counting.
11
Set OC0A/OC0B on Compare Match when up-counting.
Clear OC0A/OC0B on Compare Match when down-counting.