Datasheet

46
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once
written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a
Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See “Timed Sequences
for Changing the Configuration of the Watchdog Timer” on page 43.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the
Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an
enabled Watchdog Timer, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even
though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43.
In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCUSR – MCU Status Register” on page 44 for
description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be
cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets
during conditions causing failure, and a safe start-up after the failure.
Note: If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable proce-
dure in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or
brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the
application software should always clear the WDRF flag and the WDE control bit in the initialization routine.
• Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1, and 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different
prescaling values and their corresponding Timeout Periods are shown in Table 8-3.
Table 8-3. Watchdog Timer Prescale Select
WDP3 WDP2 WDP1 WDP0
Number of WDT Oscillator
Cycles
Typical Time-out at
V
CC
= 5.0V
0 0 0 0 2K (2048) cycles 16 ms
0 0 0 1 4K (4096) cycles 32 ms
0 0 1 0 8K (8192) cycles 64 ms
0 0 1 1 16K (16384) cycles 0.125 s
0 1 0 0 32K (32764) cycles 0.25 s
0 1 0 1 64K (65536) cycles 0.5 s
0 1 1 0 128K (131072) cycles 1.0 s
0 1 1 1 256K (262144) cycles 2.0 s
1 0 0 0 512K (524288) cycles 4.0 s
1 0 0 1 1024K (1048576) cycles 8.0 s