Datasheet

42
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Figure 8-6. Watchdog Reset During Operation
8.3 Internal Voltage Reference
ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can
be used as an input to the Analog Comparator or the ADC.
8.3.1 Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given
in “System and Reset Characteristics” on page 165. To save power, the reference is not always turned on. The ref-
erence is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL[2:0] Fuse Bits).
2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow
the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power con-
sumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is
turned off before entering Power-down mode.
8.4 Watchdog Timer
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling the Watchdog
Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-3 on page 46. The WDR –
Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled
and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If
the reset period expires without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset
Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 46.
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful
when using the Watchdog to wake-up from Power-down.
CK
CC