Datasheet

40
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
8.2.1 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “Sys-
tem and Reset Characteristics” on page 165. The POR is activated whenever V
CC
is below the detection level. The
POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V
CC
rise.
The RESET signal is activated again, without any delay, when V
CC
decreases below the detection level.
Figure 8-2. MCU Start-up, RESET
Tied to V
CC
Figure 8-3. MCU Start-up, RESET Extended Externally
8.2.2 External Reset
An External Reset is generated by a low level on the RESET
pin if enabled. Reset pulses longer than the minimum
pulse width (see “System and Reset Characteristics” on page 165) will generate a reset, even if the clock is not
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset
Threshold Voltage – V
RST
– on its positive edge, the delay counter starts the MCU after the Time-out period – t
TOUT
– has expired.
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC