Datasheet

32
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
To ensure stable operation of the MCU the calibration value should be changed in small. A variation in frequency of
more than 2% from one cycle to the next can lead to unpredicatble behavior. Changes in OSCCAL should not
exceed 0x20 for each calibration. It is required to ensure that the MCU is kept in Reset during such changes in the
clock frequency
6.5.2 CLKPR – Clock Prescale Register
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated
when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it
is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither
extend the time-out period, nor clear the CLKPCE bit.
• Bits 6:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the
master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.
The division factors are given in Table 6-15.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the
CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will
be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of eight at
start up. This feature should be used if the selected clock source has a higher frequency than the maximum fre-
quency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits
regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is
Table 6-14. Internal RC Oscillator Frequency Range
OSCCAL Value
Typical Lowest Frequency
with Respect to Nominal Frequency
Typical Highest Frequency
with Respect to Nominal Frequency
0x00 50% 100%
0x3F 75% 150%
0x7F 100% 200%
Bit 76543210
0x26 CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description