Datasheet

27
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
6.2.3 Calibrated Internal Oscillator
By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature
dependent, this clock can be very accurately calibrated by the user. See “Calibrated Internal RC Oscillator Accu-
racy” on page 164 and “Internal Oscillator Speed” on page 192 for more details. The device is shipped with the
CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 31 for more details.
This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6-6 on page
27. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed cali-
bration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of
this calibration is shown as Factory calibration in Table 21-2 on page 164.
By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on page 31, it is pos-
sible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is
shown as User calibration in Table 21-2 on page 164.
When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer
and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Cali-
bration Bytes” on page 150.
The internal oscillator can also be set to provide a 6.4 MHz clock by writing CKSEL fuses to “0011”, as shown in
Table 6-6 below. This setting is reffered to as ATtiny15 Compatibility Mode and is intended to provide a calibrated
clock source at 6.4 MHz, as in ATtiny15. In ATtiny15 Compatibility Mode the PLL uses the internal oscillator run-
ning at 6.4 MHz to generate a 25.6 MHz peripheral clock signal for Timer/Counter1 (see “8-bit Timer/Counter1 in
ATtiny15 Mode” on page 95). Note that in this mode of operation the 6.4 MHz clock signal is always divided by
four, providing a 1.6 MHz system clock.
Note: 1. The device is shipped with this option selected.
2. This setting will select ATtiny15 Compatibility Mode, where system clock is divided by four, resulting in a 1.6 MHz
clock frequency.
01 14CK + 16K (16384) CK + 4 ms 4 ms Fast rising power
10 14CK + 1K (1024) CK + 64 ms 4 ms Slowly rising power
11 14CK + 16K (16384) CK + 64 ms 4 ms Slowly rising power
Table 6-5. Start-up Times for the High Frequency PLL Clock
SUT[1:0]
Start-up Time from
Power Down
Additional Delay from
Power-On Reset (V
CC
= 5.0V)
Recommended
usage
Table 6-6. Internal Calibrated RC Oscillator Operating Modes
CKSEL[3:0] Nominal Frequency
0010
(1)
8.0 MHz
0011
(2)
6.4 MHz