Datasheet

22
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is
written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to
one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time
has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles
before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set
up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read
access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the
CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before start-
ing the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change
the EEAR Register.