Datasheet

ATtiny25/45/85 [DATASHEET]

2586Q–AVR–08/2013

5.5.3 EEDR – EEPROM Data Register

• Bits 7:0 – EEDR[7:0]: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address

given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the

EEPROM at the address given by EEAR.

5.5.4 EECR – EEPROM Control Register

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility with future AVR

devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny25/45/85 and will always read as zero.

• Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writ-

ing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value)

or to split the Erase and Write operations in two different operations. The Programming times for the different

modes are shown in Table 5-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn

bits will be reset to 0b00 unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero dis-

ables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is

ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If

EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware

clears the bit to zero after four clock cycles.

Bit 76543210

0x1D EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x1C – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

Table 5-1. EEPROM Mode Bits

EEPM1 EEPM0

Programming

Time Operation

0 0 3.4 ms Erase and Write in one operation (Atomic Operation)

0 1 1.8 ms Erase Only

1 0 1.8 ms Write Only

1 1 – Reserved for future use