Datasheet

15
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
5. AVR Memories
This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory
spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM
Memory for data storage. All three memory spaces are linear and regular.
5.1 In-System Re-programmable Flash Program Memory
The ATtiny25/45/85 contains 2/4/8K bytes On-chip In-System Reprogrammable Flash memory for program stor-
age. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1024/2048/4096 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny25/45/85 Program Counter
(PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program memory locations. “Memory Program-
ming” on page 147 contains a detailed description on Flash data serial downloading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see the LPM – Load Program
memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 11.
Figure 5-1. Program Memory Map
5.2 SRAM Data Memory
Figure 5-2 shows how the ATtiny25/45/85 SRAM Memory is organized.
The lower 224/352/607 Data memory locations address both the Register File, the I/O memory and the internal
data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and
the last 128/256/512 locations address the internal data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indi-
rect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the
indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-
register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address
registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in
the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in “Gen-
eral Purpose Register File” on page 10.
0x0000
0x03FF/0x07FF/0x0FFF
Program Memory