Datasheet

127
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC
remains high.
Figure 17-7. ADC Timing Diagram, Free Running Conversion
For a summary of conversion times, see Table 17-1.
Table 17-1. ADC Conversion Time
Condition
Sample & Hold
(Cycles from Start of Conversion)
Total Conversion Time
(Cycles)
First conversion 13.5 25
Normal conversions 1.5 13
Auto Triggered conversions 2 13.5
1 2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample & Hold
MUX and REFS
Update