Datasheet

125
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Figure 17-2. ADC Auto Trigger Logic
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.
17.5 Prescaling and Conversion Timing
Figure 17-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz
to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can
be higher than 200 kHz to get a higher sample rate. It is not recommended to use a higher input clock frequency
than 1 MHz.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU fre-
quency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the
moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as
the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the follow-
ing rising edge of the ADC clock cycle.
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START
CLK
ADC
.
.
.
.
EDGE
DETECTOR
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2 CK/4 CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START