Datasheet

104
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be ignored during ini-
tial PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The
steady state is obtained within 100 µs. After PLL lock-in it is recommended to check the PLOCK bit before enabling
PCK for Timer/Counter1.