Datasheet

194
8246B–AVR–09/11
ATtiny2313A/4313
Figure 21-7. Serial Programming Signals
Note: If the device is clocked by the internal oscillator there is no need to connect a clock source to the
CLKI pin.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation and there is no need to first execute the Chip Erase instruction. This applies for serial
programming mode, only.
The Chip Erase operation turns the content of every memory location in Flash and EEPROM
arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
• Minimum low period of serial clock:
– When f
ck
< 12MHz: > 2 CPU clock cycles
– When f
ck
>= 12MHz: 3 CPU clock cycles
• Minimum high period of serial clock:
– When f
ck
< 12MHz: > 2 CPU clock cycles
– When f
ck
>= 12MHz: 3 CPU clock cycles
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
+1.8 - 5.5V