Datasheet

19
8246B–AVR–09/11
ATtiny2313A/4313
The EEPROM memory layout is summarised in Table 5-3, below.
The internal 8MHz oscillator is used to time EEPROM operations. The frequency of the oscillator
must be within the requirements described in “OSCCAL – Oscillator Calibration Register” on
page 32.
When powered by heavily filtered supplies, the supply voltage, V
CC
, is likely to rise or fall slowly
on power-up and power-down. Slow rise and fall times may put the device in a state where it is
running at supply voltages lower than specified. To avoid problems in situations like this, see
“Preventing EEPROM Corruption” on page 20.
The EEPROM has a minimum endurance of 100,000 write/erase cycles.
5.3.1 Programming Methods
There are two methods for EEPROM programming:
• Atomic byte programming. This is the simple mode of programming, where target locations
are erased and written in a single operation. In this mode of operation the target is
guaranteed to always be erased before writing but programmin times are longer.
• Split byte programming. It is possible to split the erase and write cycle in two different
operations. This is useful when short access times are required, for example when supply
voltage is falling. In order to take advantage of this method target locations must be erased
before writing to them. This can be done at times when the system allows time-critical
operations, typically at start-up and initialisation.
The programming method is selected using the EEPROM Programming Mode bits (EEPM1 and
EEPM0) in EEPROM Control Register (EECR). See Table 5-4 on page 24. Write and erase
times are given in the same table.
Since programming takes some time the application must wait for one operation to complete
before starting the next. This can be done by either polling the EEPROM Program Enable bit
(EEPE) in EEPROM Control Register (EECR), or via the EEPROM Ready Interrupt. The
EEPROM interrupt is controlled by the EEPROM Ready Interrupt Enable (EERIE) bit in EECR.
5.3.2 Read
To read an EEPROM memory location follow the procedure below:
• Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make
sure no other EEPROM operations are in process. If set, wait to clear.
• Write target address to EEPROM Address Registers (EEARH/EEARL).
• Start the read operation by setting the EEPROM Read Enable bit (EERE) in the EEPROM
Control Register (EECR). During the read operation, the CPU is halted for four clock cycles
before executing the next instruction.
• Read data from the EEPROM Data Register (EEDR).
Table 5-3. Size of Non-Volatile Data Memory (EEPROM).
Device EEPROM Size Address Range
ATtiny2313A
128B
0x00 – 0x7F
ATtiny4313
256B
0x00 – 0xFF