Datasheet

18
8246B–AVR–09/11
ATtiny2313A/4313
flags, since they are accessible to bit-specific instructions such as SBI, CBI, SBIC, SBIS, SBRC,
and SBRS.
5.2.3 Data Memory (SRAM)
Following the general purpose register file and the I/O register file, the remaining 128/256 loca-
tions are reserved for the internal data SRAM.
There are five addressing modes available:
• Direct. This mode of addressing reaches the entire data space.
• Indirect.
• Indirect with Displacement. This mode of addressing reaches 63 address locations from the
base address given by the Y- or Z-register.
• Indirect with Pre-decrement. In this mode the address register is automatically decremented
before access. Address pointer registers (X, Y, and Z) are located in the general purpose
register file, in registers R26 to R31. See “General Purpose Register File” on page 11.
• Indirect with Post-increment. In this mode the address register is automatically incremented
after access. Address pointer registers (X, Y, and Z) are located in the general purpose
register file, in registers R26 to R31. See “General Purpose Register File” on page 11.
All addressing modes can be used on the entire volatile memory, including the general purpose
register file, the I/O register files and the data memory.
Internal SRAM is accessed in two clk
CPU
cycles, as illustrated in Figure 5-2, below.
Figure 5-2. On-chip Data SRAM Access Cycles
5.3 Data Memory (EEPROM)
ATtiny2313A/4313 contains 128 bytes of non-volatile data memory. This EEPROM is organized
as a separate data space, in which single bytes can be read and written. All access registers are
located in the I/O space.
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction