Datasheet

175
8246B–AVR–09/11
ATtiny2313A/4313
Although the least significant bit of the Z-register (Z0) should be zero for SPM, it should be noted
that the LPM instruction addresses the Flash byte-by-byte and uses Z0 as a byte select bit.
Once a programming operation is initiated, the address is latched and the Z-pointer can be used
for other operations.
19.4.2 Page Erase
To execute Page Erase:
• Set up the address in the Z-pointer
• Write “00000011” to SPMCSR
• Execute an SPM instruction within four clock cycles after writing SPMCSR
The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-regis-
ter. Other bits in the Z-pointer are ignored during this operation.
If an interrupt occurs during the timed sequence above the four cycle access cannot be guaran-
teed. In order to ensure atomic operation interrupts should be disabled before writing to
SPMCSR.
The CPU is halted during the Page Erase operation.
19.4.3 Page Load
To write an instruction word:
• Set up the address in the Z-pointer
• Set up the data in R1:R0
• Write “00000001” to SPMCSR
• Execute an SPM instruction within four clock cycles after writing SPMCSR
The content of PCWORD in the Z-register is used to address the data in the temporary buffer.
The temporary buffer will auto-erase after a Page Write operation, or by writing the RWWSRE bit
in SPMCSR. It is also erased after a system reset.
Note that it is not possible to write more than one time to each address without erasing the tem-
porary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
19.4.4 Page Write
To execute Page Write:
• Set up the address in the Z-pointer
• Write “00000101” to SPMCSR
• Execute an SPM instruction within four clock cycles after writing SPMCSR
The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in
the Z-pointer must be written to zero during this operation.
The CPU is halted during the Page Write operation.