Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Througput at 20 MHz High Endurance Non-volatile Memory segments – 1K Bytes of In-System Self-programmable Flash program memory – 64 Bytes EEPROM – 64 Bytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 Years
1. Pin Configurations Figure 1-1.
ATtiny13A 1.1 1.1.1 Pin Description VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
2. Overview The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1.
ATtiny13A The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
3. About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
ATtiny13A 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATtiny13A 4.3.1 SREG – Status Register Bit 7 6 5 4 3 2 1 0 0x3F I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATtiny13A Figure 4-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.
4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
ATtiny13A priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ Note: 4.7.
ATtiny13A 5. Memories This section describes the different memories in the ATtiny13A. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny13A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.1 In-System Reprogrammable Flash Program Memory The ATtiny13A contains 1K byte On-chip In-System Reprogrammable Flash memory for program storage.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data SRAM in the ATtiny13A are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 5-2.
ATtiny13A 5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down.
The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on page 27. The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny13A The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
5.4 I/O Memory The I/O space definition of the ATtiny13A is shown in “Register Summary” on page 158. All ATtiny13A I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
ATtiny13A 5.5.3 EECR – EEPROM Control Register Bit 7 6 5 4 3 2 1 0 0x1C – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 EECR • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny13A. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEARL Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation.
ATtiny13A 6. System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 30. The clock systems are detailed below. Figure 6-1.
6.1.4 6.2 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. Clock Sources The device has the following clock source options, selectable by Flash fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1.
ATtiny13A When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-3. Table 6-3.
When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 6-5. Table 6-5. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection SUT[1:0] Start-up Time from Power-down Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14CK(2) 01 6 CK 14CK + 4 ms Fast rising power 6 CK 14CK + 64 ms Slowly rising power (1) 10 11 Notes: Recommended Usage BOD enabled Reserved 1. The device is shipped with this option selected. 2.
ATtiny13A 6.3.1 Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency.
6.4.2 CLKPR – Clock Prescale Register Bit 7 6 5 4 3 2 1 0 CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0x26 CLKPR See Bit Description • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
ATtiny13A Table 6-8.
7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
ATtiny13A Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled).
Modules can be shut down in Idle and Active modes, significantly helping to reduce the overall power consumption. In all other sleep modes, the clock is already stopped. See “Supply Current of I/O Modules” on page 124 for examples. 7.4 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system.
ATtiny13A 7.4.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
• Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1:0 These bits select between the three available sleep modes as shown in Table 7-2 on page 34. Table 7-2. 7.5.3 Sleep Mode Select SM1 SM0 Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Reserved PRR – Power Reduction Register The Power Reduction Register provides a method to reduce power consumption by allowing peripheral clock signals to be disabled.
ATtiny13A 8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
8.2 Reset Sources The ATtiny13A has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. • Brown-out Reset.
ATtiny13A 8.2.2 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (See “System and Reset Characteristics” on page 120.) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 8-4.
8.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to “Interrupts” on page 45 for details on operation of the Watchdog Timer. Figure 8-6. Watchdog Reset During Operation CC CK 8.3 Internal Voltage Reference ATtiny13A features an internal bandgap reference.
ATtiny13A value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued. Watchdog Timer 128kHz OSCILLATOR WATCHDOG RESET WDE OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K Figure 8-7. WDP0 WDP1 WDP2 WDP3 MCU RESET WDTIF WDTIE INTERRUPT In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer.
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
ATtiny13A tion, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.
8.5 8.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs.
ATtiny13A This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDTIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. Table 8-1.
Table 8-2. Watchdog Timer Prescale Select (Continued) WDP3 WDP2 WDP1 WDP0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
ATtiny13A 9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny13A. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. 9.1 Interrupt Vectors The interrupt vectors of ATtiny13A are described in Table 9-1 below. Table 9-1. Reset and Interrupt Vectors Vector No.
9.2 External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT[5:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT[5:0] pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change interrupts PCI will trigger if any enabled PCINT[5:0] pin toggles. The PCMSK Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT[5:0] are detected asynchronously.
ATtiny13A 9.3 9.3.1 Register Description MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
9.3.3 GIFR – General Interrupt Flag Register Bit 7 6 5 4 3 2 1 0x3A – INTF0 PCIF – – – – 0 – Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
ATtiny13A 10. I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 on page 50 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2.
ATtiny13A If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one).
Figure 10-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATtiny13A The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level.
ATtiny13A The overriding signals may not be present in all port pins, but Figure 10-5 serves as a generic description applicable to all port pins in the AVR microcontroller family. Table 10-2 on page 55 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 on page 54 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2.
Table 10-3. Port B Pins Alternate Functions Port Pin Alternate Function PB5 RESET: Reset Pin dW: debugWIRE I/O ADC0: ADC Input Channel 0 PCINT5: Pin Change Interrupt, Source 5 PB4 ADC2: ADC Input Channel 2 PCINT4: Pin Change Interrupt 0, Source 4 PB3 CLKI: External Clock Input ADC3: ADC Input Channel 3 PCINT3: Pin Change Interrupt 0, Source 3 PB2 SCK: Serial Clock Input ADC1: ADC Input Channel 1 T0: Timer/Counter0 Clock Source.
ATtiny13A Table 10-5. 10.4 10.4.
10.4.
ATtiny13A 11. 8-bit Timer/Counter0 with PWM 11.1 Features • • • • • • • 11.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
11.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin.
ATtiny13A Figure 11-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count direction clear clkTn top bottom Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clkT0 in the following. Signalize that TCNT0 has reached maximum value.
Figure 11-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
ATtiny13A generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x[1:0] bit settings are reserved for certain modes of operation. See “Register Description” on page 70. 11.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes.
ATtiny13A The timing diagram for the CTC mode is shown in Figure 11-5 on page 65. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 11-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx[1:0] = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag.
for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-6 on page 66.
ATtiny13A in a constantly high or low output (depending on the polarity of the output set by the COM0A[1:0] bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x[1:0] = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x[1:0] bits to two will produce a non-inverted PWM.
ATtiny13A Figure 11-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 11-9 shows the same timing data, but with the prescaler enabled. Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 11-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 11-10.
Figure 11-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 11.9 11.9.
ATtiny13A Table 11-3 shows the COM0A[1:0] bit functionality when the WGM0[1:0] bits are set to fast PWM mode. Table 11-3. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match, set OC0A at TOP 1 1 Set OC0A on Compare Match, clear OC0A at TOP Note: Description 1.
Table 11-5. Compare Output Mode, non-PWM Mode COM0B1 COM0B0 Description 0 0 Normal port operation, OC0B disconnected. 0 1 Toggle OC0B on Compare Match 1 0 Clear OC0B on Compare Match 1 1 Set OC0B on Compare Match Table 11-6 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM mode. Table 11-6. Compare Output Mode, Fast PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected.
ATtiny13A • Bits 1:0 – WGM0[1:0]: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 11-8 on page 73. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 64).
• Bit 6 – FOC0B: Force Output Compare B The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B[1:0] bits setting. Note that the FOC0B bit is implemented as a strobe.
ATtiny13A 11.9.4 OCR0A – Output Compare Register A Bit 7 6 5 0x36 4 3 2 1 0 OCR0A[7:0] OCR0A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 11.9.
11.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0x38 – – – – OCF0B OCF0A TOV0 0 – Read/Write R R R R R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIFR0 • Bits 7:4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B.
ATtiny13A 12. Timer/Counter Prescaler 12.1 Overview The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either f CLK_I/O /8, f CLK_I/O /64, fCLK_I/O/256, or fCLK_I/O/1024. 12.
sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 12-2.
ATtiny13A 13. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
13.2 13.2.1 Register Description ADCSRB – ADC Control and Status Register Bit 7 6 5 4 3 2 1 0 0x03 – ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator.
ATtiny13A • Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 13-2 on page 81. Table 13-2. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.
14. Analog to Digital Converter 14.1 Features • • • • • • • • • • • • • 14.2 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.
ATtiny13A The ADC is connected to a 4-channel Analog Multiplexer which allows four single-ended voltage inputs constructed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. Internal reference voltages of nominally 1.1V or VCC are provided On-chip. 14.
Figure 14-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
ATtiny13A The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 14-6 below. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. Figure 14-6.
ATtiny13A For a summary of conversion times, see Table 14-1. Table 14-1. ADC Conversion Time Condition Conversion Time (Cycles) First conversion 13.5 25 Normal conversions 1.5 13 2 13.5 Auto Triggered conversions 14.6 Sample & Hold (Cycles from Start of Conversion) Changing Channel or Reference Selection The MUXn and REFS[1:0] bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access.
14.6.2 14.7 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V reference. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
ATtiny13A The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 14-9. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 14-10.
ATtiny13A • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 14-11. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 14-12.
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB. 14.
ATtiny13A • Bits 1:0 – MUX[1:0]: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 14-3 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Table 14-3. Input Channel Selections MUX[1:0] 14.12.
• Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. • Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 14-4. 14.12.3 14.12.3.
ATtiny13A The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC[9:0]: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 92. 14.12.
15. debugWIRE On-chip Debug System 15.1 Features • • • • • • • • • • 15.
ATtiny13A When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 15.
16. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”). The Program memory is updated in a page by page fashion.
ATtiny13A If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 16.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. Note: 16.4 The CPU is halted during the Page Write operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. 16.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the fuses and lock bits from software will also be prevented during the EEPROM write operation.
ATtiny13A To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 See sections “Program And Data Memory Lock Bits” on page 103 and “Fuse Bytes” on page 104 for more information on fuse and lock bits. 16.
16.9 16.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit 7 6 5 4 3 2 1 0 0x37 – – – CTPB RFLB PGWRT PGERS SELFPRGEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCSR • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and always read as zero.
ATtiny13A 17. Memory Programming This section describes how ATtiny13A memories can be programmed. 17.1 Program And Data Memory Lock Bits ATtiny13A provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 17-2 on page 103. The lock bits can be erased to “1” with the Chip Erase command, only. Program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed, even if the lock bits are set.
17.2 Fuse Bytes The ATtiny13A has two fuse bytes. Table 17-3 on page 104 and Table 17-4 on page 104 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 17-3.
ATtiny13A Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Program the fuse bits before programming the lock bits. The status of the fuse bits is not affected by Chip Erase. Fuse bits can also be read by the device firmware. See section “Reading Fuse and Lock Bits from Firmware” on page 100. 17.2.1 17.3 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode.
17.6 Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 17-1. Figure 17-1. Serial Programming and Verify +1.8 - 5.5V RESET PB5 GND Note: VCC PB2 SCK PB1 MISO PB0 MOSI If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.
ATtiny13A 17.6.1 Serial Programming Algorithm When writing serial data to the ATtiny13A, data is clocked on the rising edge of SCK. When reading data from the ATtiny13A, data is clocked on the falling edge of SCK. See Figure 18-4 on page 122 and Figure 18-3 on page 122 for timing details. To program and verify the ATtiny13A in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 17-9 on page 108): 1.
. Table 17-8. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol 17.6.2 Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms Serial Programming Instruction set The instruction set is described in Table 17-9. Table 17-9.
ATtiny13A Table 17-9. Serial Programming Instruction Set (Continued) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Read fuse low/high byte. Bit “0” = programmed, “1” = unprogrammed. See “Fuse Bytes” on page 104 for details. Read Fuse Byte 0101 H000 0000 H000 xxxx xxxx oooo oooo Write Fuse Byte 1010 1100 1010 H000 xxxx xxxx iiii iiii Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.
Table 17-10. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode Pin Name I/O Function SDI PB0 I Serial Data Input SII PB1 I Serial Instruction Input SDO PB2 O Serial Data Output SCI PB3 I Serial Clock Input (min. 220ns period) The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220 ns. Table 17-11. Pin Values Used to Enter Programming Mode 17.7.
ATtiny13A 6. Wait until Vcc actually reaches 4.5 - 5.5V before giving any serialinstructions on SDI/SII. 7. Exit Programming mode by power the device down or by bringing RESET pin to 0V. Table 17-12. High-voltage Reset Characteristics RESET Pin High-voltage Threshold Minimum High-voltage Period for Latching Prog_enable VCC VHVRST tHVRST 4.5V 12V 100 ns 5.5V 12 100 ns Supply Voltage 17.7.2 High-Voltage Serial Programming Instruction set The instruction set is described in Table 17-13.
Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13A (Continued) Instruction Format Instruction Load EEPROM Page Buffer Program EEPROM Page Write EEPROM Byte Load “Read EEPROM” Command Read EEPROM Byte Write Fuse Low Bits Instr.1/5 Instr.2/6 Instr.3 Instr.
ATtiny13A Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13A (Continued) Instruction Format Instruction Read Signature Bytes Instr.1/5 Instr.2/6 Instr.3 Instr.
17.8.2 Programming the Flash The Flash is organized in pages, see Table 17-9 on page 108. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: 1. Load Command “Write Flash” (see Table 17-13 on page 111). 2. Load Flash Page Buffer. 3. Load Flash High Address and Program Page. Wait after Instr.
ATtiny13A Figure 17-4. High-voltage Serial Programming Waveforms SDI PB0 MSB LSB SII PB1 MSB LSB SDO PB2 SCI PB3 17.8.3 MSB 0 LSB 1 2 3 4 5 6 7 8 9 10 Programming the EEPROM The EEPROM is organized in pages, see Table 18-9 on page 122. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 17-13 on page 111): 1.
17.8.7 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 17-13 on page 111. 17.8.8 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn VCC power off.
ATtiny13A 18. Electrical Characteristics 18.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Table 18-1. Symbol DC Characteristics, TA = -40°C to +85°C (Continued) Parameter Supply Current, Active Mode (7) ICC Supply Current, Idle Mode (7) Supply Current, Power-Down Mode (8) Notes: Typ(1) Max Units f = 1MHz, VCC = 2V 0.2 0.35 mA f = 4MHz, VCC = 3V 1.2 1.8 mA f = 8MHz, VCC = 5V 3.6 6 mA f = 1MHz, VCC = 2V 0.03 0.2 mA f = 4MHz, VCC = 3V 0.2 1 mA f = 8MHz, VCC = 5V 0.7 3 mA WDT enabled, VCC = 3V 3.9 10 µA WDT disabled, VCC = 3V 0.15 2 µA Condition Min 1.
ATtiny13A 18.4 Clock Characteristics 18.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 19-59 on page 154, Figure 19-60 on page 154, Figure 19-61 on page 155, Figure 19-62 on page 155, Figure 19-63 on page 156, and Figure 19-64 on page 156. Table 18-2.
18.5 System and Reset Characteristics Table 18-4. Symbol Reset, Brown-out, and Internal Voltage Characteristics Parameter VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin (1) Condition Min Typ 0.2 VCC VCC = 1.8V VCC = 3V VCC = 5V Max Units 0.
ATtiny13A 18.6 Analog Comparator Characteristics Table 18-7. Analog Comparator Characteristics, TA = -40°C to +85°C Symbol Parameter Condition VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.8 - 5.
18.8 Serial Programming Characteristics Figure 18-3. Serial Programming Timing MOSI SCK tSLSH tSHOX tOVSH tSHSL MISO Figure 18-4. Serial Programming Waveform SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 18-9. Symbol Parameter 1/tCLCL Oscillator Frequency Oscillator Period tCLCL 1/tCLCL 1/tCLCL tCLCL tSHSL Oscillator Period tOVSH MOSI Setup to SCK High tSHOX MOSI Hold after SCK High Typ VCC = 1.8 – 5.
ATtiny13A 18.9 High-voltage Serial Programming Characteristics Figure 18-5. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) tIVSH SCI (PB3) tSLSH tSHIX tSHSL SDO (PB2) tSHOV Table 18-10. High-voltage Serial Programming Characteristics TA = 25°C, VCC = 5.
19. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
ATtiny13A 19.2 Current Consumption in Active Mode Figure 19-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 1 ICC (mA) 0.9 0.8 5.5 V 0.7 5.0 V 0.6 4.5 V 0.5 4.0 V 0.4 3.3 V 0.3 2.7 V 0.2 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 19-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 12 10 5.5 V 8 ICC (mA) 5.0 V 4.5 V 6 4.0 V 4 3.
Figure 19-3. Active Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 9.6 MHz 8 7 6 85 °C 25 °C -40 °C ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4.8 MHz 3.5 85 °C 25 °C -40 °C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny13A Figure 19-5. Active Supply Current vs. VCC (Internal WDT Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL WD OSCILLATOR, 128 KHz 0.12 25 °C -40 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-6. Active Supply Current vs. VCC (32 kHz External Clock) ACTIVE SUPPLY CURRENT vs. VCC 32 KHz EXTERNAL CLOCK, PRR = 0xFF 0.03 85 °C 25 °C -40 °C 0.025 ICC (mA) 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
19.3 Current Consumption in Idle Mode Figure 19-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0.1 5.5 V 0.08 5.0 V 4.5 V 0.06 ICC (mA) 4.0 V 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 19-8. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 2 5.5 V 1.5 5.0 V ICC (mA) 4.5 V 1 4.0 V 3.3 V 0.5 2.7 V 1.
ATtiny13A Figure 19-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 9.6 MHz 1.6 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4.8 MHz 0.7 85 °C 0.6 25 °C -40 °C ICC (mA) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 19-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL WD OSCILLATOR, 128 KHz 0.025 -40 °C 25 °C 85 °C 0.02 ICC (mA) 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-12. Idle Supply Current vs. VCC (32 kHz External Clock) IDLE SUPPLY CURRENT vs. VCC 32 KHz EXTERNAL OSCILLATOR, PRR=0xFF 0.006 0.005 85 °C 25 °C -40 °C ICC (mA) 0.004 0.003 0.002 0.001 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny13A 19.4 Current Consumption in Power-down Mode Figure 19-13. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 1 0.9 0.8 85 °C -40 °C 0.7 ICC (uA) 0.6 25 °C 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-14. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 10 9 -40 °C 8 25 °C 85 °C 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.
19.5 Current Consumption in Reset Figure 19-15. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.08 5.5 V 0.07 5.0 V 0.06 4.5 V ICC (mA) 0.05 4.0 V 0.04 3.3 V 0.03 2.7 V 0.02 1.8 V 0.01 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 19-16. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs.
ATtiny13A 19.6 Current Consumption of Peripheral Units Figure 19-17. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 30 25 85 °C 25 °C -40 °C ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-18. ADC Current vs. VCC ADC CURRENT vs. VCC f = 1.0 MHz 400 85 °C 25 °C -40 °C 350 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 19-19. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC f = 1.0 MHz 100 90 85 °C 80 25 °C -40 °C 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-20. Programming Current vs. VCC PROGRAMMING CURRENT vs. VCC 9000 8000 -40 °C ICC (uA) 7000 6000 25 °C 5000 85 °C 4000 3000 2000 1000 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny13A 19.7 Pull-up Resistors Figure 19-21. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.8V 60 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) Figure 19-22. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 3V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Figure 19-23. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 160 85 °C 140 25 °C -40 °C 120 IOP (uA) 100 80 60 40 20 0 0 1 2 3 4 5 6 VOP (V) Figure 19-24. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.
ATtiny13A Figure 19-25. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 3V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 3V 80 70 60 IRESET (uA) 50 40 30 20 10 25 °C -40 °C 85 °C 0 0 0,5 1 1,5 2 2,5 3 3,5 VRESET (V) Figure 19-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
19.8 Output Driver Strength (Low Power Pins) Figure 19-27. VOH: I/O Pin Output Voltage vs. Source Current (Low Power Pins, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT LOW POWER PINS, VCC = 1.8V 2 1.8 1.6 1.4 VOH (V) 1.2 -40 °C 1 25 °C 0.8 85 °C 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (mA) Figure 19-28. VOH: I/O Pin Output Voltage vs. Source Current (Low Power Pins, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT LOW POWER PINS, VCC = 3V 3.
ATtiny13A Figure 19-29. VOH: I/O Pin Output Voltage vs. Source Current (Low Power Pins, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT LOW POWER PINS, VCC = 5V 5.2 5 VOH (V) 4.8 4.6 -40 °C 4.4 25 °C 85 °C 4.2 4 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 19-30. VOL: I/O Pin Output Voltage vs. Sink Current (Low Power Pins, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT LOW POWER PINS, VCC = 1.8V 3 2.5 85 °C 25 °C VOL (V) 2 1.5 1 -40 °C 0.5 0 0 0.5 1 1.5 2 2.
Figure 19-31. VOL: I/O Pin Output Voltage vs. Sink Current (Low Power Pins, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT LOW POWER PINS, VCC = 3V 0.9 85 °C 0.8 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 19-32. VOL: I/O Pin Output Voltage vs. Sink Current (Low Power Pins, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT LOW POWER PINS, VCC = 5V 1.2 85 °C 1 25 °C VOL (V) 0.8 -40 °C 0.6 0.4 0.
ATtiny13A 19.9 Output Driver Strength (Regular Pins) Figure 19-33. VOH: I/O Pin Output Voltage vs. Source Current (VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 1.8V 2 1.8 1.6 1.4 -40 °C 25 °C 85 °C VOH (V) 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 IOH (mA) Figure 19-34. VOH: I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.1 2.9 -40 °C 25 °C 85 °C 2.7 VOH (V) 2.5 2.3 2.1 1.9 1.7 1.
Figure 19-35. VOH: I/O Pin Output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT V CC = 5V 5.2 5 V OH (V) 4.8 4.6 -40 °C 25 °C 85 °C 4.4 4.2 4 0 2 4 6 8 10 12 14 16 18 20 I OH (mA) Figure 19-36. VOL: I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 1.8V 0.5 85 °C 0.45 0.4 25 °C 0.35 VOL (V) 0.3 -40 °C 0.25 0.2 0.15 0.1 0.
ATtiny13A Figure 19-37. VOL: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0.45 0.4 85 °C 0.35 25 °C 0.3 VOL (V) -40 °C 0.25 0.2 0.15 0.1 0.05 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 19-38. VOL: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0.7 0.6 85 °C VOL (V) 0.5 25 °C -40 °C 0.4 0.3 0.2 0.
Figure 19-39. VOH: Reset Pin as I/O, Output Voltage vs. Source Current (VCC = 1.8V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 1.8V 1,6 1,4 1,2 VOH (V) 1 0,8 0,6 -40 °C 0,4 25 °C 85 °C 0,2 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 IOH (mA) Figure 19-40. VOH: Reset Pin as I/O, Output Voltage vs. Source Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs.
ATtiny13A Figure 19-41. VOH: Reset Pin as I/O, Output Voltage vs. Source Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 4,5 4 3,5 -40 °C 25 °C 85 °C VOH (V) 3 2,5 2 1,5 1 0,5 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 IOH (mA) Figure 19-42. VOL: Reset Pin as I/O, Output Voltage vs. Sink Current (VCC = 1.8V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 1.
Figure 19-43. VOL: Reset Pin as I/O, Output Voltage vs. Sink Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 1,6 1,4 1,2 85 °C VOL (V) 1 0,8 25 °C 0,6 -40 °C 0,4 0,2 0 0 0,5 1 1,5 2 2,5 3 IOL (mA) Figure 19-44. VOL: Reset Pin as I/O, Output Voltage vs. Sink Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs.
ATtiny13A 19.10 Input Thresholds and Hysteresis (for I/O Ports) Figure 19-45. VIH: Input Threshold Voltage vs. VCC (I/O Pin, Read as '1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, I/O PIN READ AS '1' 3.5 85 °C 25 °C -40 °C 3 Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-46. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as '0') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, I/O PIN READ AS '0' 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.
Figure 19-47. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) I/O PIN INPUT HYSTERESIS vs. VCC 0.6 -40 °C 0.5 Input Hysteresis (V) 25 °C 0.4 85 °C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-48. VIH: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as '1') RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIH, RESET READ AS '1' 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny13A Figure 19-49. VIL: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as '0') RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIL, RESET READ AS '0' 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-50. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin as I/O) RESET PIN AS IO, INPUT HYSTERESIS vs. VCC V IL , I/O PIN READ AS "0" 1 0.9 0.8 0.7 Input Hysteresis (V) -40 °C 0.6 0.5 25 °C 0.4 85 °C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.
19.11 BOD, Bandgap and Reset Figure 19-51. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 4.3V 4.4 VCC RISING Threshold (V) 4.35 4.3 VCC FALLING 4.25 4.2 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 19-52. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 2.7V 2.8 VCC RISING Threshold (V) 2.75 VCC FALLING 2.7 2.65 2.
ATtiny13A Figure 19-53. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 1.8V 1.9 1.85 Threshold (V) VCC RISING VCC FALLING 1.8 1.75 1.7 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 19-54. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. VCC 1.14 Bandgap Voltage (V) 1.12 85 °C 25 °C 1.1 -40 °C 1.08 1.06 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 19-55. VIH: Reset Input Threshold Voltage vs. VCC (Reset Pin Read as '1') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, I/O PIN READ AS '1' 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-56. VIL: Reset Input Threshold Voltage vs. VCC (Reset Pin Read as '0') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, I/O PIN READ AS '0' 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny13A Figure 19-57. VIH-VIL: Reset Input Pin Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 1 0.9 Input Hysteresis (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -40 °C 25 °C 85 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-58. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs.
19.12 Internal Oscillator Speed Figure 19-59. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10 9.9 5.5 V 4.5 V 9.8 2.7 V 1.8 V Frequency (MHz) 9.7 9.6 9.5 9.4 9.3 9.2 9.1 9 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 19-60. Calibrated 9.6 MHz RC Oscillator Frequency vs. VCC CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 10 85 °C Frequency (MHz) 9.8 9.6 25 °C 9.4 9.2 -40 °C 9 1.5 2 2.5 3 3.
ATtiny13A Figure 19-61. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE VCC = 3V 20 18 25 °C 16 Frequency (MHz) 14 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 OSCCAL Figure 19-62. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4.8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5 1.8 V 5.5 V 2.7 V 4.0 V 4.9 Frequency (MHz) 4.8 4.7 4.6 4.5 4.4 4.
Figure 19-63. Calibrated 4.8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4.8MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 5.2 5 Frequency (MHz) 85 °C 4.8 25 °C 4.6 -40 °C 4.4 4.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-64. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4.8MHz RC OSCILLATOR FREQUENCY vs.
ATtiny13A Figure 19-65. 128 kHz Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 116000 114000 Frequency (Hz) 112000 -40 °C 25 °C 110000 108000 106000 85 °C 104000 102000 100000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-66. 128 kHz Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 115000 114000 113000 Frequency (kH) 112000 111000 110000 1.8 V 109000 2.7 V 108000 107000 4.0 V 106000 5.
20.
ATtiny13A Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.ome of the Status Flags are cleared by writing a logical one to them.
21.
ATtiny13A Mnemonics Operands Description Operation Flags ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V #Clocks 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
22. Ordering Information Speed (MHz) Power Supply (V) 20 Notes: 1.8 - 5.
ATtiny13A 23. Packaging Information 23.1 8P3 E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL MIN NOM A b2 b3 b 4 PLCS Side View L 0.210 NOTE 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 0.100 BSC eA 0.300 BSC 0.115 3 3 e L Notes: MAX 0.130 4 0.
23.2 8S2 C 1 E E1 L N θ TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 θ 0° 8° 1.27 BSC 2 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position.
ATtiny13A 23.3 8S1 4 2 3 1 H N Top View e B A D COMMON DIMENSIONS (Unit of Measure = mm) Side View A2 C L SYMBOL MIN NOM MAX A – – 1.75 B – – 0.51 C – – 0.25 D – – 5.00 E – – 4.00 e E End View NOTE 1.27 BSC H – – 6.20 L – – 1.27 Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2010-10-20 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.
23.4 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOTE 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
ATtiny13A 23.5 10M1 D y Pin 1 ID SIDE VIEW E TOP VIEW A1 A D1 K COMMON DIMENSIONS (Unit of Measure = mm) 1 2 b E1 e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 2.90 3.00 3.10 D1 1.40 – 1.75 E 2.90 3.00 3.10 E1 2.20 – 2.70 e L BOTTOM VIEW NOTE 0.50 L 0.30 – 0.50 y – – 0.08 K 0.20 – – Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5. 2. The terminal #1 ID is a Lasser-marked Feature.
24. Errata The revision letters in this section refer to the revision of the ATtiny13A device. 24.1 ATtiny13A Rev. G – H • EEPROM can not be written below 1.9 Volt 1. EEPROM can not be written below 1.9 Volt Writing the EEPROM at VCC below 1.9 volts might fail. Problem Fix/Workaround Do not write the EEPROM when VCC is below 1.9 volts. 24.2 ATtiny13A Rev. E – F These device revisions were not sampled. 24.3 ATtiny13 Rev. A – D These device revisions were referred to as ATtiny13/ATtiny13V.
ATtiny13A 25. Datasheet Revision History Please note that page numbers in this section refer to the current version of this document and may not apply to previous versions. 25.1 Rev. 8126F – 05/12 1. Updated Table 10-5 on page 57. 2. Updated order codes on page 162. 25.2 Rev. 8126E – 07/10 1. Updated description in Section 6.4.2 “CLKPR – Clock Prescale Register” on page 28. 2. Adjusted notes in Table 18-1, “DC Characteristics, TA = -40°C to +85°C,” on page 117. 3. Updated plot order in Section 19.
– “Speed” on page 118 5. Update tables: – “DC Characteristics, TA = -40°C to +85°C” on page 117 – “Calibration Accuracy of Internal RC Oscillator” on page 119 – “Reset, Brown-out, and Internal Voltage Characteristics” on page 120 – “ADC Characteristics, Single Ended Channels. TA = -40°C to +85°C” on page 121 – “Serial Programming Characteristics, TA = -40°C to +85°C” on page 122 6.
ATtiny13A Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 Overview ................................................................................................... 4 2.1 3 4 5 6 7 Pin Description ..................................................................................................
8 9 7.4 Minimizing Power Consumption ......................................................................32 7.5 Register Description ........................................................................................33 System Control and Reset .................................................................... 35 8.1 Resetting the AVR ...........................................................................................35 8.2 Reset Sources ..............................................
ATtiny13A 13.2 Register Description ........................................................................................80 14 Analog to Digital Converter .................................................................. 82 14.1 Features ..........................................................................................................82 14.2 Overview ..........................................................................................................82 14.3 Operation ................
17.4 Signature Bytes .............................................................................................105 17.5 Page Size ......................................................................................................105 17.6 Serial Programming .......................................................................................106 17.7 High-Voltage Serial Programming .................................................................109 17.
ATtiny13A 23.3 8S1 ................................................................................................................165 23.4 20M1 ..............................................................................................................166 23.5 10M1 ..............................................................................................................167 24 Errata ..................................................................................................... 168 24.
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