Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 97
ATtiny4/5/9/10
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise
Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power
consumption.
14.8 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 14-8 An analog source applied to ADCn is sub-
jected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the
ADC. When the channel is selected, the source must drive the S/H (sample and hold) capacitor through the series resis-
tance (combined resistance in the input path).
Figure 14-8. Analog Input Circuitry
The capacitor in Figure 14-8 depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic
capacitance inside the device. The value given is worst case.
The ADC is optimized for analog signals with an output impedance of approximately 10 k, or less. With such sources, the
sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time
the source needs to charge the S/H capacitor. This can vary widely. The user is recommended to only use low impedance
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
Signal components higher than the Nyquist frequency (f
ADC
/2) should not be present to avoid distortion from unpredictable
signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the sig-
nals as inputs to the ADC.
14.9 Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements.
When conversion accuracy is critical, the noise level can be reduced by applying the following techniques:
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• Place bypass capacitors as close to V
CC
and GND pins as possible.
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as described in Section 14.7
on page 96. A good system design with properly placed, external bypass capacitors does reduce the need for using ADC
Noise Reduction Mode
ADCn
I
IH
1..100 kohm
C
S/H
= 14 pF
V
CC
/2
I
IL