Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 96
ATtiny4/5/9/10
14.6 Changing Channel
The MUXn bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random
access. This ensures that the channel selection only takes place at a safe point during the conversion. The channel is con-
tinuously updated until a conversion is started. Once the conversion starts, the channel selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion com-
pletes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is
written. The user is thus advised not to write new channel selection values to ADMUX until one ADC clock cycle after
ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when
updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in
this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely
updated in the following ways:
• When ADATE or ADEN is cleared.
• During conversion, minimum one ADC clock cycle after the trigger event.
• After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
14.6.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is
selected:
• In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be
changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to
complete before changing the channel selection.
• In Free Running mode, always select the channel before starting the first conversion. The channel selection may be
changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion
to complete, and then change the channel selection. Since the next conversion has already started automatically, the
next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection.
14.6.2 ADC Voltage Reference
The reference voltage of the ADC determines the conversion range, which in this case is limited to 0V (V
GND
) and V
REF
=
V
cc
. Channels that exceed V
REF
will result in codes saturated at 0xFF.
14.7 ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core
and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this
feature, the following procedure should be used:
• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC
conversion complete interrupt must be enabled.
• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.
• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute
the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is
complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when
the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed.