Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 87
ATtiny4/5/9/10
12.11.9 TIFR0 – Timer/Counter Interrupt Flag Register 0
• Bits 7:6, 4:3 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero
when the register is written.
• Bit 5 – ICF0: Timer/Counter0, Input Capture Flag
This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register (ICR0) is set by the
WGM03:0 to be used as the TOP value, the ICF0 flag is set when the counter reaches the TOP value.
ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF0 can be cleared by
writing a logic one to its bit location.
• Bit 2 – OCF1B: Timer/Counter0, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output Compare Register B (OCR0B).
Note that a Forced Output Compare (0B) strobe will not set the OCF0B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can
be cleared by writing a logic one to its bit location.
• Bit 1 – OCF0A: Timer/Counter0, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output Compare Register A (OCR0A).
Note that a Forced Output Compare (1A) strobe will not set the OCF0A flag.
OCF0A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF0A can
be cleared by writing a logic one to its bit location.
• Bit 0 – TOV0: Timer/Counter0, Overflow Flag
The setting of this flag is dependent of the WGM03:0 bits setting. In Normal and CTC modes, the TOV0 flag is set when the
timer overflows. See Table 12-5 on page 83 for the TOV0 flag behavior when using another WGM03:0 bit setting.
TOV0 is automatically cleared when the Timer/Counter0 Overflow Interrupt Vector is executed. Alternatively, TOV0 can be
cleared by writing a logic one to its bit location.
12.11.10 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the
PSR bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can
be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR bit is cleared
by hardware, and the Timer/Counter start counting.
Bit 765432 1 0
0x2A
– –ICF0– – OCF0B OCF0A TOV0 TIFR0
Read/Write R R R/W R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x2F TSM
– – – – – – PSR GTCCR
Read/Write R/W R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0