Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 79
ATtiny4/5/9/10
replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV0 flag at
BOTTOM.
Figure 12-14. Timer/Counter Timing Diagram, no Prescaling
Figure 12-15 on page 79 shows the same timing data, but with the prescaler enabled.
Figure 12-15. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
12.10 Accessing 16-bit Registers
The TCNT0, OCR0A/B, and ICR0 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-
bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for tem-
porary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers
within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit
register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value
New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
Tn
(clk
I/O
/1)
clk
I/O
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)