Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 78

ATtiny4/5/9/10

TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic

values.

12.9 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

) is therefore shown as a clock enable signal in the

following figures. The figures include information on when interrupt flags are set, and when the OCR0x Register is updated

with the OCR0x buffer value (only for modes utilizing double buffering). Figure 12-12 on page 78 shows a timing diagram

for the setting of OCF0x.

Figure 12-12. Timer/Counter Timing Diagram, Setting of OCF0x, no Prescaling

Figure 12-13 on page 78 shows the same timing data, but with the prescaler enabled.

Figure 12-13. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f

clk_I/O

/8)

Figure 12-14 on page 79 shows the count sequence close to TOP in various modes. When using phase and frequency cor-

rect PWM mode the OCR0x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be

clk

(clk

I/O

/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2