Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 77

ATtiny4/5/9/10

Figure 12-11. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set at the same timer clock cycle as the OCR0x Registers are updated with the

double buffer value (at BOTTOM). When either OCR0A or ICR0 is used for defining the TOP value, the OC0A or ICF0 flag

set when TCNT0 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the

Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur

between the TCNT0 and the OCR0x.

As Figure 12-11 on page 77 shows the output generated is, in contrast to the phase correct mode, symmetrical in all peri-

ods. Since the OCR0x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be

equal. This gives symmetrical output pulses and is therefore frequency correct.

Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A Register is

free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively changed by chang-

ing the TOP value, using the OCR0A as TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins.

Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by set-

ting the COM0x1:0 to three (See Table 12-4 on page 82). The actual OC0x value will only be visible on the port pin if the

data direction for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the

OC0x Register at the compare match between OCR0x and TCNT0 when the counter increments, and clearing (or setting)

the OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for

the output when using phase and frequency correct PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in the

phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set equal to

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnxPFCPWM

clk_I/O

2NTOP

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