Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 75

ATtiny4/5/9/10

Figure 12-10. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. When either OCR0A or ICR0 is

used for defining the TOP value, the OC0A or ICF0 flag is set accordingly at the same timer clock cycle as the OCR0x Reg-

isters are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time

the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the

Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur

between the TCNT0 and the OCR0x. Note that when using fixed TOP values, the unused bits are masked to zero when

any of the OCR0x Registers are written. As the third period shown in Figure 12-10 on page 75 illustrates, changing the

TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The rea-

son for this can be found in the time of update of the OCR0x Register. Since the OCR0x update occurs at TOP, the PWM

period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value,

while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the

period will differ in length. The difference in length gives the unsymmetrical result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the

TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between

the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins. Setting the

COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the

COM0x1:0 to three (See Table 12-4 on page 82). The actual OC0x value will only be visible on the port pin if the data direc-

tion for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x

OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the

output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnxPCPWM

clk_I/O

2NTOP

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