Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 73

ATtiny4/5/9/10

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or OCR0A. The minimum res-

olution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is 16-bit (ICR0 or OCR0A set to

MAX). The PWM resolution in bits can be calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF,

0x01FF, or 0x03FF (WGM03:0 = 5, 6, or 7), the value in ICR0 (WGM03:0 = 14), or the value in OCR0A (WGM03:0 = 15).

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure

12-9 on page 73. The figure shows fast PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is in

the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x

and TCNT0. The OC0x interrupt flag will be set when a compare match occurs.

Figure 12-9. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. In addition the OC0A or ICF0 flag is

set at the same timer clock cycle as TOV0 is set when either OCR0A or ICR0 is used for defining the TOP value. If one of

the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the

Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur

between the TCNT0 and the OCR0x. Note that when using fixed TOP values the unused bits are masked to zero when any

of the OCR0x Registers are written.

The procedure for updating ICR0 differs from updating OCR0A when used for defining the TOP value. The ICR0 Register

is not double buffered. This means that if ICR0 is changed to a low value when the counter is running with none or a low

prescaler value, there is a risk that the new ICR0 value written is lower than the current value of TCNT0. The result will then

be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value

(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR0A Register however, is dou-

ble buffered. This feature allows the OCR0A I/O location to be written anytime. When the OCR0A I/O location is written the

value written will be put into the OCR0A Buffer Register. The OCR0A Compare Register will then be updated with the value

in the Buffer Register at the next timer clock cycle the TCNT0 matches TOP. The update is done at the same timer clock

cycle as the TCNT0 is cleared and the TOV0 flag is set.

FPWM

TOP 1+log

2log

-----------------------------------=

TCNTn

OCRnx/TOP Update and

TOVn Interrupt Flag Set and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 7

Period

2 3 4 5 6 8

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)