Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 71
ATtiny4/5/9/10
OC0x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode,
but there are some exceptions. See Table 12-2 on page 82, Table 12-3 on page 82 and Table 12-4 on page 82 for details.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that
some COM0x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 81
The COM0x1:0 bits have no effect on the Input Capture unit.
12.7.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the
COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next compare
match. For compare output actions in the non-PWM modes refer to Table 12-2 on page 82. For fast PWM mode refer to
Table 12-3 on page 82, and for phase correct and phase and frequency correct PWM refer to Table 12-4 on page 82.
A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the 0x strobe bits.
12.8 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination
of the Waveform Generation mode (WGM03:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode
bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0
bits control whether the output should be set, cleared or toggle at a compare match (“Compare Match Output Unit” on page
70)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 78.
12.8.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM03:0 = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value
(MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag
(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a
17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears
the TOV0 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal
mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external
events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow inter-
rupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate
waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
12.8.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM03:0 = 4 or 12), the OCR0A or ICR0 Register are used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches either the
OCR0A (WGM03:0 = 4) or the ICR0 (WGM03:0 = 12). The OCR0A or ICR0 define the top value for the counter, hence also
its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of
counting external events.
The timing diagram for the CTC mode is shown in Figure 12-8 on page 72. The counter value (TCNT0) increases until a
compare match occurs with either OCR0A or ICR0, and then counter (TCNT0) is cleared.