Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 69
ATtiny4/5/9/10
Figure 12-6. Output Compare Unit, Block Diagram
The OCR0x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Nor-
mal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR0x Compare Register to either TOP or BOTTOM of the counting sequence. The syn-
chronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. The con-
tent of the OCR0x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update
this register automatically as the TCNT0 and ICR0 Register). Therefore OCR0x is not read via the high byte temporary reg-
ister (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the
OCR0x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte
(OCR0xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated
by the value written. Then when the low byte (OCR0xL) is written to the lower eight bits, the high byte will be copied into the
upper 8-bits of either the OCR0x buffer or OCR0x Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 79.
12.6.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force
Output Compare (0x) bit. Forcing compare match will not set the OCF0x flag or reload/clear the timer, but the OC0x pin will
be updated as if a real compare match had occurred (the COM01:0 bits settings define whether the OC0x pin is set,
cleared or toggled).
12.6.2 Compare Match Blocking by TCNT0 Write
All CPU writes to the TCNT0 Register will block any compare match that occurs in the next timer clock cycle, even when
the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt
when the Timer/Counter clock is enabled.
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
COMnx1:0WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM