Datasheet
2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 68
ATtiny4/5/9/10
that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICR0 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP0 pin.
12.5.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is moni-
tored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC0) bit in Timer/Counter Control Register B
(TCCR0B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change
applied to the input, to the update of the ICR0 Register. The noise canceler uses the system clock and is therefore not
affected by the prescaler.
12.5.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming
events. The time between two events is critical. If the processor has not read the captured value in the ICR0 Register
before the next event occurs, the ICR0 will be overwritten with a new value. In this case the result of the capture will be
incorrect.
When using the Input Capture interrupt, the ICR0 Register should be read as early in the interrupt handler routine as possi-
ble. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent
on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during opera-
tion, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the
edge sensing must be done as early as possible after the ICR0 Register has been read. After a change of the edge, the
Input Capture Flag (ICF0) must be cleared by software (writing a logical one to the I/O bit location). For measuring fre-
quency only, the clearing of the ICF0 flag is not required (if an interrupt handler is used).
12.6 Output Compare Units
The 16-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0x). If TCNT equals OCR0x
the comparator signals a match. A match will set the Output Compare Flag (OCF0x) at the next timer clock cycle. If
enabled (OCIE0x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF0x flag is automatically
cleared when the interrupt is executed. Alternatively the OCF0x flag can be cleared by software by writing a logical one to
its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set
by the Waveform Generation mode (WGM03:0) bits and Compare Output mode (COM0x1:0) bits. The TOP and BOTTOM
signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of oper-
ation (“Modes of Operation” on page 71).
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In
addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform
Generator.
Figure 12-6 on page 69 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indi-
cates the device number (n = 0
for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B). The elements of the
block diagram that are not directly a part of the Output Compare unit are gray shaded.