Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 66
ATtiny4/5/9/10
TOP Signalize that TCNT0 has reached maximum value.
BOTTOM Signalize that TCNT0 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) containing the upper eight bits
of the counter, and Counter Low (TCNT0L) containing the lower eight bits. The TCNT0H Register can only be indirectly
accessed by the CPU. When the CPU does an access to the TCNT0H I/O location, the CPU accesses the high byte tempo-
rary register (TEMP). The temporary register is updated with the TCNT0H value when the TCNT0L is read, and TCNT0H is
updated with the temporary register value when TCNT0L is written. This allows the CPU to read or write the entire 16-bit
counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to
the TCNT0 Register when the counter is counting that will give unpredictable results. The special cases are described in
the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk
T
0
).
The clk
T
0
can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no
clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, inde-
pendent of whether clk
T
0
is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM03:0) located in the
Timer/Counter Control Registers A and B (TCCR0A and TCCR0B). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the Output Compare outputs OC0x. For more details about
advanced counting sequences and waveform generation, see “Modes of Operation” on page 71.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM03:0 bits. TOV0
can be used for generating a CPU interrupt.
12.5 Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicat-
ing time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP0 pin. The
time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the
time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 12-5 on page 67. The elements of the block dia-
gram that are not directly a part of the Input Capture unit are gray shaded. The lower case “n” in register and bit names
indicates the Timer/Counter number.