Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 65
ATtiny4/5/9/10
detector logic. The registers are clocked at the positive edge of the internal system clock (clk
I/O
). The latch is transparent in
the high period of the internal system clock.
The edge detector generates one clk
T
0
pulse for each positive (CS2:0 = 7) or negative (CS2:0 = 6) edge it detects.
Figure 12-3. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been
applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, other-
wise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The
external clock must be guaranteed to have less than half the system clock frequency (f
ExtClk
< f
clk_I/O
/2) given a 50/50%
duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the
sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle
caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of
an external clock source is less than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
12.4 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 12-4 on page 65
shows a block diagram of the counter and its surroundings.
Figure 12-4. Counter Unit Block Diagram
Signal description (internal signals):
Count Increment or decrement TCNT0 by 1.
Direction Select between increment and decrement.
Clear Clear TCNT0 (set all bits to zero).
clk
T
0
Timer/Counter clock.
Tn_sync
(To Clock
Select Logic)
Edge DetectorSynchronization
DQDQ
LE
DQ
Tn
clk
I/O
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn