Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 63

ATtiny4/5/9/10

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 12-1 on page 62. For actual placement of I/O

pins, refer to “Pinout of ATtiny4/5/9/10” on page 8. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown

in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 81.

Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter

number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in

a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.

12.2.1 Registers

The Timer/Counter (TCNT0), Output Compare Registers (OCR0A/B), and Input Capture Register (ICR0) are all 16-bit reg-

isters. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the

section “Accessing 16-bit Registers” on page 79. The Timer/Counter Control Registers (TCCR0A/B) are 8-bit registers and

have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer

Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR

and TIMSK are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock

Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The

Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clkT

0).

The double buffered Output Compare Registers (OCR0A/B) are compared with the Timer/Counter value at all time. The

result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Out-

put Compare pin (OC0A/B). See “Output Compare Units” on page 68. The compare match event will also set the Compare

Match Flag (OCF0A/B) which can be used to generate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the

Input Capture pin (ICP0) or on the Analog Comparator pins (See “Analog Comparator” on page 89). The Input Capture unit

includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR0A Reg-

ister, the ICR0 Register, or by a set of fixed values. When using OCR0A as TOP value in a PWM mode, the OCR0A

ing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR0 Register can be used as an

alternative, freeing the OCR0A to be used as PWM output.

12.2.2 Definitions

The following definitions are used extensively throughout the section:

12.3 Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock

Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter control Register B

(TCCR0B). For details on clock sources and prescaler, see section “Prescaler”.

Table 12-1. Definitions

Constant Description

BOTTOM The counter reaches BOTTOM when it becomes 0x00

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255)

TOP

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the

value stored in the OCR0A Register. The assignment depends on the mode of operation