Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 47

ATtiny4/5/9/10

Figure 10-1. Timing of pin change interrupts

10.3 Register Description

10.3.1 EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

• Bits 7:2 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bits 1:0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are

set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 10-2. The value on the

INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock

Bit 76543210

0x15

– – – – – – ISC01 ISC00 EICRA

Read/Write RRRRRRR/WR/W

Initial Value 0 0 0 0 0 0 0 0

clk

PCINT(0)

pin_lat

pin_sync

pcint_in_(0)

pcint_syn

pcint_setflag

PCIF