Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 40
ATtiny4/5/9/10
Figure 9-5. Watchdog Reset During Operation
9.3 Watchdog Timer
The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. See Figure 9-6. By controlling the
Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 9-2 on page 42. The WDR –
Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when
a device reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period
expires without another Watchdog Reset, the ATtiny4/5/9/10 resets and executes from the Reset Vector. For timing details
on the Watchdog Reset, refer to Table 9-3 on page 43.
Figure 9-6. Watchdog Timer
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using
the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels
are selected by the fuse WDTON as shown in Table 9-1 on page 41. See “Procedure for Changing the Watchdog Timer
Configuration” on page 41 for details.
CK
CC
OSC/2K OSC/4K OSC/8K
OSC/16K OSC/32K OSC/64K
OSC/128K OSC/256K
OSC/512K
OSC/1024K
MCU RESET
WATCHDOG
PRESCALER
128 kHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
MUX