Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 36
ATtiny4/5/9/10
8.4.2 PRR – Power Reduction Register
• Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 1 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator
cannot use the ADC input MUX when the ADC is shut down.
The ADC is available in ATtiny5/10, only.
• Bit 0 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will
continue like before the shutdown.
Bit 7 6 5 4 3 2 1 0
0x35
– – – – – – PRADC PRTIM0 PRR
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0