Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 35

ATtiny4/5/9/10

8.3.4 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to

ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clk

I/O

) is stopped, the input buffers of the

device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the

input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable

and Sleep Modes” on page 54 for details on which pins are enabled. If the input buffer is enabled and the input signal is left

floating or has an analog signal level close to V

/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V

/2 on an

input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital

Input Disable Register (DIDR0). Refer to “DIDR0 – Digital Input Disable Register 0” on page 90 for details.

8.4 Register Description

8.4.1 SMCR – Sleep Mode Control Register

The SMCR Control Register contains control bits for power management.

• Bits 7:4 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bits 3:1 – SM2..SM0: Sleep Mode Select Bits 2..0

These bits select between available sleep modes, as shown in Table 8-2.

Note: 1. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC

• Bit 0 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To

avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep

Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

Bit 76543210

0x3A

– – – – SM2 SM1 SM0 SE SMCR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 8-2. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle

0 0 1 ADC noise reduction

(1)

0 1 0 Power-down

0 1 1 Reserved

1 0 0 Standby

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved