Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 34
ATtiny4/5/9/10
8.1.3 Power-down Mode
When bits SM2:0 are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the
oscillator is stopped, while the external interrupts, and the watchdog continue operating (if enabled). Only a watchdog
reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all gener-
ated clocks, allowing operation of asynchronous modules only.
8.1.4 Standby Mode
When bits SM2:0 are written to 100, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-down with the exception that the oscillator is kept running. This reduces wake-up time, because the oscillator is
already running and doesn't need to be started up.
8.2 Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 36, provides a method to reduce
power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is stopped then:
• The current state of the peripheral is frozen.
• The associated registers can not be read or written.
• Resources used by the peripheral will remain occupied.
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the peripheral
and puts it in the same state as before shutdown.
Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See
“Supply Current of I/O Modules” on page 130 for examples. In all other sleep modes, the clock is already stopped.
8.3 Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR Core controlled system. In
general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as pos-
sible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following
modules may need special consideration when trying to achieve the lowest possible power consumption.
8.3.1 Analog Comparator
When entering Idle mode, the analog comparator should be disabled if not used. In the power-down mode, the analog com-
parator is automatically disabled. See “Analog Comparator” on page 89 for further details.
8.3.2 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any
sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. See “Analog to
Digital Converter” on page 91 for details on ADC operation.
The ADC is available in ATtiny5/10, only.
8.3.3 Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled,
it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-
nificantly to the total current consumption. Refer to “Watchdog Timer” on page 40 for details on how to configure the
Watchdog Timer.