Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 33
ATtiny4/5/9/10
8.1 Sleep Modes
Figure 7-1 on page 27 presents the different clock systems and their distribution in ATtiny4/5/9/10. The figure is helpful in
selecting an appropriate sleep mode. Table 8-1 shows the different sleep modes and their wake up sources.
Note: 1. The ADC is available in ATtiny5/10, only
2. For INT0, only level interrupt.
To enter any of the four sleep modes, the SE bits in SMCR must be written to logic one and a SLEEP instruction must be
executed. The SM2:0 bits in the SMCR register select which sleep mode (Idle, ADC Noise Reduction, Standby or Power-
down) will be activated by the SLEEP instruction. See Table 8-2 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles
in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP.
The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during
sleep mode, the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the
MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 46 for details.
8.1.1 Idle Mode
When bits SM2:0 are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing
the analog comparator, timer/counter, watchdog, and the interrupt system to continue operating. This sleep mode basically
halts clk
CPU
and clk
NVM
, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow. If
wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the
ACD bit in “ACSR – Analog Comparator Control and Status Register” on page 89. This will reduce power consumption in
idle mode. If the ADC is enabled (ATtiny5/10, only), a conversion starts automatically when this mode is entered.
8.1.2 ADC Noise Reduction Mode
When bits SM2:0 are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping
the CPU but allowing the ADC, the external interrupts, and the watchdog to continue operating (if enabled). This sleep
mode halts clk
I/O
, clk
CPU
, and clk
NVM
, while allowing the other clocks to run.
This mode improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled,
a conversion starts automatically when this mode is entered.
This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC.
Table 8-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes
Sleep Mode
Active Clock Domains Oscillators Wake-up Sources
clk
CPU
clk
NVM
clk
IO
clk
ADC
(1)
Main Clock Source Enabled INT0 and Pin Change ADC
(1)
Other I/O Watchdog Interrupt VLM Interrupt
Idle XX X XXXXX
ADC Noise Reduction X X X
(2)
XXX
Standby X X
(2)
X
Power-down X
(2)
X