Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 32
ATtiny4/5/9/10
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits can be
written at run-time to vary the clock frequency and suit the application requirements. As the prescaler divides the master
clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The division factors are given in
Table 7-4.
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the CLKPS
bits:
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the desired value to CLKPS bits
At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has a fre-
quency higher than the maximum allowed the application software must make sure a sufficient division factor is used. To
make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler settings.
8. Power Management and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power
applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s
requirements.
Table 7-4. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0000 1
0001 2
0010 4
0 0 1 1 8 (default)
0100 16
0101 32
0110 64
0 1 1 1 128
1 0 0 0 256
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved