Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 26
ATtiny4/5/9/10
6.3 I/O Memory
The I/O space definition of the ATtiny4/5/9/10 is shown in “Register Summary” on page 157.
All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST
instructions, enabling data transfer between the 16 general purpose working registers and the I/O space. I/O Registers
within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. See document “AVR Instruction Set” and sec-
tion “Instruction Set Summary” on page 159 for more details. When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI instructions will only operate on
the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work on
registers in the address range 0x00 to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.