Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 21
ATtiny4/5/9/10
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending inter-
rupts, as shown in the following example.
Note: See “Code Examples” on page 15.
5.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the
Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Pro-
gram Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three
clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the
interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter
(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
5.8 Register Description
5.8.1 CCP – Configuration Change Protection Register
• Bits 7:0 – CCP[7:0] – Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written with the correct signature.
After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles. All interrupts
are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU, and any pending
interrupts will be executed according to their priority.
When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is enabled,
while CCP[7:1] will always read as zero.
Table 5-1 shows the signatures that are in recognised.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
Bit 76543210
0x3C CCP[7:0] CCP
Read/Write WWWWWWWR/W
Initial Value00000000
Table 5-1. Signatures Recognised by the Configuration Change Protection Register
Signature Group Description
0xD8 IOREG: CLKMSR, CLKPSR, WDTCSR Protected I/O register