Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 16
ATtiny4/5/9/10
5. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct pro-
gram execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.
5.1 Architectural Overview
Figure 5-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and
buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instruc-
tions to be executed in every clock cycle. The program memory is In-System reprogrammable Flash memory.
The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle access time.
This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the
Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling
efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
16 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
Timer/Counter 0
ADC