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 2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 1

Features

• High Performance, Low Power AVR

8-Bit Microcontroller

• Advanced RISC Architecture

– 54 Powerful Instructions – Most Single Clock Cycle Execution

– 16 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 12 MIPS Throughput at 12 MHz

• Non-volatile Program and Data Memories

– 512/1024 Bytes of In-System Programmable Flash Program Memory

– 32 Bytes Internal SRAM

– Flash Write/Erase Cycles: 10,000

– Data Retention: 20 Years at 85C / 100 Years at 25C

• Peripheral Features

–QTouch

Library Support for Capacitive Touch Sensing (1 Channel)

– One 16-bit Timer/Counter with Prescaler and Two PWM Channels

– Programmable Watchdog Timer with Separate On-chip Oscillator

– 4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only)

– On-chip Analog Comparator

• Special Microcontroller Features

– In-System Programmable (at 5V, only)

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Supply Voltage Level Monitor with Interrupt and Reset

– Internal Calibrated Oscillator

• I/O and Packages

– Four Programmable I/O Lines

– 6-pin SOT and 8-pad UDFN

tinyAVR

Data Sheet

ATtiny4/5/9/10

Introduction

The ATtiny4/5/9/10 is a low power, CMOS 8-bit microcontrollers based on the AVR

enhanced RISC archi-

tecture. The ATtiny4/5/9/10 is a 6/8-pins device ranging from 512 Bytes to 1024 Bytes Flash, with 32 Bytes

SRAM. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching

one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power

consumption versus processing speed.

Summary of content (173 pages)

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ATtiny4/5/9/10 tinyAVR® Data Sheet Introduction The ATtiny4/5/9/10 is a low power, CMOS 8-bit microcontrollers based on the AVR® enhanced RISC architecture. The ATtiny4/5/9/10 is a 6/8-pins device ranging from 512 Bytes to 1024 Bytes Flash, with 32 Bytes SRAM. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
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ATtiny4/5/9/10 • Operating Voltage: – 1.8 – 5.5V • Programming Voltage: – 5V • Speed Grade – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 8 MHz @ 2.7 – 5.5V – 0 – 12 MHz @ 4.5 – 5.5V • Industrial and Extended Temperature Ranges • Low Power Consumption – Active Mode: • 200µA at 1MHz and 1.8V – Idle Mode: • 25µA at 1MHz and 1.8V – Power-down Mode: • < 0.1µA at 1.8V  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 Table Of Contents 1 Pin Configurations ................................................................................... 8 1.1 2 3 Ordering Information ............................................................................... 9 2.1 ATtiny4 .............................................................................................................. 9 2.2 ATtiny5 ............................................................................................................ 10 2.
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ATtiny4/5/9/10 7.5 8 9 Register Description ........................................................................................ 30 Power Management and Sleep Modes ................................................. 32 8.1 Sleep Modes.................................................................................................... 33 8.2 Power Reduction Register ............................................................................... 34 8.3 Minimizing Power Consumption .................
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ATtiny4/5/9/10 14 Analog to Digital Converter ................................................................... 91 14.1 Features .......................................................................................................... 91 14.2 Overview.......................................................................................................... 91 14.3 Operation......................................................................................................... 91 14.
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ATtiny4/5/9/10 17.6 Analog Comparator Characteristics............................................................... 128 17.7 ADC Characteristics (ATtiny5/10, only) ......................................................... 128 17.8 Serial Programming Characteristics .............................................................. 129 18 Typical Characteristics ........................................................................ 130 18.1 Supply Current of I/O Modules ................................
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ATtiny4/5/9/10 23.8 Rev. 8127B – 08/09....................................................................................... 168 23.9 Rev. 8127A – 04/09....................................................................................... 169  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 1. Pin Configurations Figure 1-1. Pinout of ATtiny4/5/9/10 SOT-23 (PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0 GND (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1 2 3 6 5 4 PB3 (RESET/PCINT3/ADC3) VCC PB2 (T0/CLKO/PCINT2/INT0/ADC2) UDFN (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 NC NC GND 1.1 1 2 3 4 8 7 6 5 PB2 (T0/CLKO/PCINT2/INT0/ADC2) VCC PB3 (RESET/PCINT3/ADC3) PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0) Pin Description 1.1.1 VCC Supply voltage. 1.1.2 Ground. GND 1.1.3 Port B (PB3..
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ATtiny4/5/9/10 2. Ordering Information 2.1 ATtiny4 Supply Voltage Speed(1) Temperature Package(2) 12 MHz Industrial (-40C to 85C)(4) 6ST1 ATtiny4-TSHR(5) 8MA4 ATtiny4-MAHR(6) 10 MHz Extended (-40C to 125C)(6) 6ST1 ATtiny4-TS8R(5) 1.8 – 5.5V Notes: Ordering Code(3) 1. For speed vs. supply voltage, see section 17.3 “Speed” on page 125. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS).
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ATtiny4/5/9/10 2.2 ATtiny5 Supply Voltage Speed(1) Temperature Package(2) 12 MHz Industrial (-40C to 85C)(4) 6ST1 ATtiny5-TSHR(5) 8MA4 ATtiny5-MAHR(6) 10 MHz Extended (-40C to 125C)(6) 6ST1 ATtiny5-TS8R(5) 1.8 – 5.5V Notes: Ordering Code(3) 1. For speed vs. supply voltage, see section 17.3 “Speed” on page 125. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3.
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ATtiny4/5/9/10 2.3 ATtiny9 Supply Voltage Speed(1) Temperature Package(2) 12 MHz Industrial (-40C to 85C)(4) 6ST1 ATtiny9-TSHR(5) 8MA4 ATtiny9-MAHR(6) 10 MHz Extended (-40C to 125C)(6) 6ST1 ATtiny9-TS8R(5) 1.8 – 5.5V Notes: Ordering Code(3) 1. For speed vs. supply voltage, see section 17.3 “Speed” on page 125. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3.
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ATtiny4/5/9/10 2.4 ATtiny10 Supply Voltage Speed(1) Temperature Package(2) Ordering Code(3) 12 MHz Industrial (-40C to 85C)(4) 6ST1 ATtiny10-TSHR(5) 8MA4 ATtiny10-MAHR(6) 10 MHz Extended (-40C to 125C)(6) 6ST1 ATtiny10-TS8R(5) 1.8 – 5.5V Notes: 1. For speed vs. supply voltage, see section 17.3 “Speed” on page 125. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3.
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ATtiny4/5/9/10 3. Overview ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure 3-1.
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ATtiny4/5/9/10 four software selectable power saving modes. ATtiny5/10 are also equipped with a four-channel, 8-bit Analog to Digital Converter (ADC). Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC.
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ATtiny4/5/9/10 4. General Information 4.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at www.microchip.com 4.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
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ATtiny4/5/9/10 5. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.1 Architectural Overview Figure 5-1.
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ATtiny4/5/9/10 in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
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ATtiny4/5/9/10 Figure 5-2. AVR CPU General Purpose Working Registers 7 0 R16 R17 Note: General R18 Purpose … Working R26 X-register Low Byte Registers R27 X-register High Byte R28 Y-register Low Byte R29 Y-register High Byte R30 Z-register Low Byte R31 Z-register High Byte A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny4/5/9/10 implement only 16 registers. For reasons of compatibility the registers are numbered R16...R31, not R0...R15.
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ATtiny4/5/9/10 5.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.
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ATtiny4/5/9/10 Figure 5-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 5.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the program memory space.
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ATtiny4/5/9/10 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) Note: See “Code Examples” on page 15. 5.7.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum.
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ATtiny4/5/9/10 5.8.2 Bit SPH and SPL — Stack Pointer Register 15 14 13 12 11 10 9 8 0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND 5.8.
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ATtiny4/5/9/10 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 159 for detailed information.  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 6. Memories This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the program memory space and the data memory space. 6.1 In-System Re-programmable Flash Program Memory The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16.
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ATtiny4/5/9/10 Figure 6-1. Data Memory Map (Byte Addressing) I/O SPACE 0x0000 ... 0x003F SRAM DATA MEMORY 0x0040 ... 0x005F (reserved) 0x0060 ... 0x3EFF NVM LOCK BITS 0x3F00 ... 0x3F01 (reserved) 0x3F02 ... 0x3F3F CONFIGURATION BITS 0x3F40 ... 0x3F41 (reserved) 0x3F42 ... 0x3F7F CALIBRATION BITS 0x3F80 ... 0x3F81 (reserved) 0x3F82 ... 0x3FBF DEVICE ID BITS 0x3FC0 ... 0x3FC3 (reserved) 0x3FC4 ... 0x3FFF FLASH PROGRAM MEMORY (reserved) 0x4000 ... 0x41FF/0x43FF 0x4400 ... 0xFFFF 6.2.
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ATtiny4/5/9/10 6.3 I/O Memory The I/O space definition of the ATtiny4/5/9/10 is shown in “Register Summary” on page 157. All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between the 16 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
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ATtiny4/5/9/10 7. Clock System Figure 7-1 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 32. The clock systems is detailed below. Figure 7-1.
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ATtiny4/5/9/10 7.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. The ADC is available in ATtiny5/10, only. 7.2 Clock Sources All synchronous clock signals are derived from the main clock.
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ATtiny4/5/9/10 7.2.4 Switching Clock Source The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings Register” on page 30. When switching between any clock sources, the clock system ensures that no glitch occurs in the main clock. 7.2.5 Default Clock Source The calibrated internal 8 MHz oscillator is always selected as main clock when the device is powered up or has been reset.
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ATtiny4/5/9/10 7.4 Starting 7.4.1 Starting from Reset The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps, as follows. 1. The first step after the reset source has been released consists of the device counting the reset start-up time.
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ATtiny4/5/9/10 • Bit 7:2 – Res: Reserved Bits These bits are reserved and always read zero. • Bit 1:0 – CLKMS[1:0]: Clock Main Select Bits These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock. The clock system ensures glitch free switching of the main clock source. The main clock alternatives are shown in Table 7-3. Table 7-3.
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ATtiny4/5/9/10 • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written at run-time to vary the clock frequency and suit the application requirements. As the prescaler divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The division factors are given in Table 7-4. Table 7-4.
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ATtiny4/5/9/10 8.1 Sleep Modes Figure 7-1 on page 27 presents the different clock systems and their distribution in ATtiny4/5/9/10. The figure is helpful in selecting an appropriate sleep mode. Table 8-1 shows the different sleep modes and their wake up sources. Table 8-1.
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ATtiny4/5/9/10 8.1.3 Power-down Mode When bits SM2:0 are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the oscillator is stopped, while the external interrupts, and the watchdog continue operating (if enabled). Only a watchdog reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only. 8.1.
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ATtiny4/5/9/10 8.3.4 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clkI/O) is stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
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ATtiny4/5/9/10 8.4.2 PRR – Power Reduction Register Bit 7 6 5 4 3 2 1 0 0x35 – – – – – – PRADC PRTIM0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR • Bits 7:2 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 1 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.
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ATtiny4/5/9/10 9. System Control and Reset 9.1 Resetting the AVR During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 9-1 shows the reset logic.
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ATtiny4/5/9/10 A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after VCC rise. The reset signal is activated again, without any delay, when VCC decreases below the detection level. Figure 9-2. MCU Start-up, RESET Tied to VCC V CC V POT RESET V RST TIME-OUT t TOUT INTERNAL RESET Figure 9-3.
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ATtiny4/5/9/10 When VLM is active and voltage at VCC is above the selected trigger level operation will be as normal and the VLM can be shut down for a short period of time. If voltage at VCC drops below the selected threshold the VLM will either flag an interrupt or generate a reset, depending on the configuration. When the VLM has been configured to generate a reset at low supply voltage it will keep the device in reset as long as VCC is below the reset level.
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ATtiny4/5/9/10 Figure 9-5. Watchdog Reset During Operation CC CK 9.3 Watchdog Timer The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. See Figure 9-6. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 9-2 on page 42. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs.
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ATtiny4/5/9/10 Table 9-1. WDT Configuration as a Function of the Fuse Settings of WDTON Safety Level WDTON WDT Initial State How to Disable the WDT How to Change Time-out Unprogrammed 1 Disabled Protected change sequence No limitations Programmed 2 Enabled Always enabled Protected change sequence 9.3.1 Procedure for Changing the Watchdog Timer Configuration The sequence for changing configuration differs between the two safety levels, as follows: 9.3.1.
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ATtiny4/5/9/10 9.4 Register Description 9.4.1 WDTCSR – Watchdog Timer Control and Status Register Bit 7 6 5 4 3 2 1 0 0x31 WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCSR • Bit 7 – WDIF: Watchdog Timer Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
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ATtiny4/5/9/10 • Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 9-3 on page 43. Table 9-3. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
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ATtiny4/5/9/10 Table 9-4. Setting the Trigger Level of Voltage Level Monitor. VLM2:0 Label Description 000 VLM0 Voltage Level Monitor disabled 001 VLM1L 010 VLM1H Triggering generates a regular Power-On Reset (POR). The VLM flag is not set 011 VLM2 100 VLM3 Triggering sets the VLM Flag (VLMF) and generates a VLM interrupt, if enabled 101 110 Not allowed 111 For VLM voltage levels, see Table 17-6 on page 127. 9.4.
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ATtiny4/5/9/10 10. Interrupts This section describes the specifics of the interrupt handling in ATtiny4/5/9/10. For a general explanation of the AVR interrupt handling, see “Reset and Interrupt Handling” on page 20. 10.1 Interrupt Vectors Interrupt vectors of ATtiny4/5/9/10 are described in Table 10-1 below. Table 10-1. Reset and Interrupt Vectors Vector No.
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ATtiny4/5/9/10 0x000B RESET: ldi 0x000C out SPH,r16 0x000D ldi r16, low(RAMEND) ; to top of RAM 0x000E out SPL,r16 0x000F sei 0x0010 ... ... 10.2 r16, high(RAMEND); Main program start ; Set Stack Pointer ; Enable interrupts External Interrupts External Interrupts are triggered by the INT0 pin or any of the PCINT3..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT3..0 pins are configured as outputs.
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ATtiny4/5/9/10 Figure 10-1. Timing of pin change interrupts pin_lat PCINT(0) D pcint_in_(0) Q clk 0 pcint_syn pcint_setflag PCIF pin_sync LE x PCINT(0) in PCMSK(x) clk clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 10.3 Register Description 10.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
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ATtiny4/5/9/10 period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 10-2. Interrupt 0 Sense Control ISC01 ISC00 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request.
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ATtiny4/5/9/10 10.3.4 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 0x12 – – – – – – – PCIE0 Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 PCICR • Bits 7:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT3..
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ATtiny4/5/9/10 11. I/O Ports 11.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors.
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ATtiny4/5/9/10 11.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 11-2 shows a functional description of one I/Oport pin, here generically called Pxn. Figure 11-2.
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ATtiny4/5/9/10 The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). The pull-up resistor is activated, if the PUExn is written logic one.
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ATtiny4/5/9/10 Figure 11-3. Switching Between Input and Output in Break-Before-Make-Mode SYSTEM CLK r16 0x02 r17 0x01 INSTRUCTIONS out DDRx, r16 nop PORTx DDRx 0x55 0x02 0x01 Px0 Px1 out DDRx, r17 0x01 tri-state tri-state tri-state intermediate tri-state cycle intermediate tri-state cycle 11.2.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit.
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ATtiny4/5/9/10 When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 11-5 on page 54. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 11-5. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd 11.2.
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ATtiny4/5/9/10 11.2.7 Program Example The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from 2 to 3 as input with a pull-up assigned to port pin 2. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example ...
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ATtiny4/5/9/10 Figure 11-6.
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ATtiny4/5/9/10 Table 11-2 on page 57 summarizes the function of the overriding signals. The pin and port indexes from Figure 11-6 on page 56 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 11-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
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ATtiny4/5/9/10 11.3.1 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 11-3 on page 58. Table 11-3.
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ATtiny4/5/9/10 • PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source for pin change interrupt 0. • TPICLK: Serial Programming Clock. • Port B, Bit 2 – ADC2/CLKO/INT0/PCINT2/T0 • ADC2: Analog to Digital Converter, Channel 2 (ATtiny5/10, only) • CLKO: System Clock Output. The system clock can be output on pin PB2. The system clock will be output if CKOUT bit is programmed, regardless of the PORTB2 and DDB2 settings.
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ATtiny4/5/9/10 Table 11-5. Overriding Signals for Alternate Functions in PB1..
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ATtiny4/5/9/10 11.4.3 PORTB – Port B Data Register Bit 7 6 5 4 3 2 1 0 0x02 – – – – PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 11.4.4 DDRB – Port B Data Direction Register Bit 7 6 5 4 3 2 1 0 0x01 – – – – DDB3 DDB2 DDB1 DDB0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 11.4.
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ATtiny4/5/9/10 12. 16-bit Timer/Counter0 12.1 • • • • • • • • • • • Features True 16-bit Design, Including 16-bit PWM Two Independent Output Compare Units Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceler Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Four independent interrupt Sources (TOV0, OCF0A, OCF0B, and ICF0) 12.
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ATtiny4/5/9/10 A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 12-1 on page 62. For actual placement of I/O pins, refer to “Pinout of ATtiny4/5/9/10” on page 8. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 81. Most register and bit references in this section are written in general form.
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ATtiny4/5/9/10 12.3.1 Prescaler The Timer/Counter can be clocked directly by the system clock (by setting the CS2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. See Figure 12-2 for an illustration of the prescaler unit. Figure 12-2. Prescaler for Timer/Counter0 clk I/O Clear PSR10 T0 Synchronization clkT0 Note: 1.
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ATtiny4/5/9/10 detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT0 pulse for each positive (CS2:0 = 7) or negative (CS2:0 = 6) edge it detects. Figure 12-3. T0 Pin Sampling D Tn Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.
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ATtiny4/5/9/10 TOP BOTTOM Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) containing the upper eight bits of the counter, and Counter Low (TCNT0L) containing the lower eight bits. The TCNT0H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT0H I/O location, the CPU accesses the high byte temporary register (TEMP).
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ATtiny4/5/9/10 Figure 12-5. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) WRITE ACO* Analog Comparator ACIC* TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.
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ATtiny4/5/9/10 that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR0 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP0 pin. 12.5.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme.
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ATtiny4/5/9/10 Figure 12-6. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCR0x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
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ATtiny4/5/9/10 12.6.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using any of the Output Compare channels, independent of whether the Timer/ Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation.
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ATtiny4/5/9/10 OC0x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. See Table 12-2 on page 82, Table 12-3 on page 82 and Table 12-4 on page 82 for details. The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation.
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ATtiny4/5/9/10 Figure 12-8. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF0A or ICF0 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
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ATtiny4/5/9/10 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX).
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ATtiny4/5/9/10 Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A Register is free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR0A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins.
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ATtiny4/5/9/10 Figure 12-10. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM.
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ATtiny4/5/9/10 The extreme values for the OCR0x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 12.8.
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ATtiny4/5/9/10 Figure 12-11. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV0) is set at the same timer clock cycle as the OCR0x Registers are updated with the double buffer value (at BOTTOM).
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ATtiny4/5/9/10 TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 12.9 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR0x Register is updated with the OCR0x buffer value (only for modes utilizing double buffering).
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ATtiny4/5/9/10 replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV0 flag at BOTTOM. Figure 12-14. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value Figure 12-15 on page 79 shows the same timing data, but with the prescaler enabled.
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ATtiny4/5/9/10 the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR0A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte.
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ATtiny4/5/9/10 The code example returns the TCNT0 value in the r17:r16 register pair. The following code example shows how to do an atomic write of the TCNT0 Register contents. Writing any of the OCR0A/ B or ICR0 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT0: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT0 to r17:r16 out TCNT0H,r17 out TCNT0L,r16 ; Restore global interrupt flag out SREG,r18 ret Note: See “Code Examples” on page 15.
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ATtiny4/5/9/10 When OC0A or OC0B is connected to the pin, the function of COM0x1:0 bits depends on the WGM03:0 bits. Table 12-2 shows the COM0x1:0 bit functionality when the WGM03:0 bits are set to a Normal or CTC (non-PWM) Mode. Table 12-2.
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ATtiny4/5/9/10 Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (“Modes of Operation” on page 71). Table 12-5.
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ATtiny4/5/9/10 • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR0B is written. • Bits 4:3 – WGM03:2: Waveform Generation Mode See “TCCR0A – Timer/Counter0 Control Register A” on page 81. • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits set the clock source to be used by the Timer/Counter, see Figure 12-12 and Figure 12-13. Table 12-6.
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ATtiny4/5/9/10 12.11.4 Bit TCNT0H and TCNT0L – Timer/Counter0 7 6 5 4 3 0x29 TCNT0[15:8] 0x28 TCNT0[7:0] 2 1 0 TCNT0H TCNT0L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT0H and TCNT0L, combined TCNT0) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
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ATtiny4/5/9/10 12.11.7 Bit ICR0H and ICR0L – Input Capture Register 0 7 6 5 4 3 0x23 ICR0[15:8] 0x22 ICR0[7:0] 2 1 0 ICR0H ICR0L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the ICP0 pin (or optionally on the Analog Comparator output for Timer/Counter0). The Input Capture can be used for defining the counter TOP value.
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ATtiny4/5/9/10 12.11.9 TIFR0 – Timer/Counter Interrupt Flag Register 0 Bit 7 6 5 4 3 2 1 0 0x2A – – ICF0 – – OCF0B OCF0A TOV0 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR0 • Bits 7:6, 4:3 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when the register is written.
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ATtiny4/5/9/10 • Bit 0 – PSR: Prescaler 0 Reset Timer/Counter 0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 13. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
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ATtiny4/5/9/10 • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
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ATtiny4/5/9/10 14. Analog to Digital Converter 14.1 • • • • • • • • • • • • Features 8-bit Resolution 0.5 LSB Integral Non-linearity  1 LSB Absolute Accuracy 65µs Conversion Time 15 kSPS at Full Resolution Four Multiplexed Single Ended Input Channels Input Voltage Range: 0 – VCC Supply Voltage Range: 2.5V – 5.5V Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler 14.
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ATtiny4/5/9/10 Figure 14-1. Analog to Digital Converter Block Schematic ADCSRB ADCL ADIE ADEN ADPS0 ADPS1 ADPS2 ADATE ADCSRA ADSC MUX1 ADC IRQ TRIGGER SELECT PRESCALER ADIF CHANNEL START DECODER ADC7:0 MUX0 ADMUX ADTS2:0 INTERRUPT FLAGS 8-BIT DATA BUS CONVERSION LOGIC VREF VCC 8-BIT DAC + ADC3 ADC2 ADC1 SAMPLE & HOLD COMPARATOR INPUT MUX ADC0 14.
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ATtiny4/5/9/10 Figure 14-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC data register. The first conversion must be started by writing a logical one to bit ADSC bit in ADCSRA.
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ATtiny4/5/9/10 When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles, as summarized in Table 14-1 on page 95. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. See Figure 14-4. Figure 14-4.
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ATtiny4/5/9/10 Figure 14-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCL Conversion Result Conversion Prescaler Reset Complete Sample & Hold Prescaler MUX Reset Update In Free Running mode (see Figure 14-7), a new conversion will be started immediately after the conversion completes, while ADSC remains high. Figure 14-7.
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ATtiny4/5/9/10 14.6 Changing Channel The MUXn bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channel selection only takes place at a safe point during the conversion. The channel is continuously updated until a conversion is started. Once the conversion starts, the channel selection is locked to ensure a sufficient sampling time for the ADC.
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ATtiny4/5/9/10 Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 14.
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ATtiny4/5/9/10 14.10 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x00 to 0x01) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 14-9.
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ATtiny4/5/9/10 • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0xFE to 0xFF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 14-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
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ATtiny4/5/9/10 Figure 14-12. Differential Non-linearity (DNL) Output Code 0xFF 1 LSB DNL 0x00 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
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ATtiny4/5/9/10 14.12 Register Description ADMUX – ADC Multiplexer Selection Register 14.12.1 Bit 7 6 5 4 3 2 1 0 0x1B – – – – – – MUX1 MUX0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bits 7:2 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 1:0 – MUX1:0: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 14-2 for details..
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ATtiny4/5/9/10 • Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is requested if the ADIE bit is set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one, the ADC Conversion Complete Interrupt request is enabled.
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ATtiny4/5/9/10 Table 14-4. ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0 1 0 0 Timer/Counter 0 Overflow 1 0 1 Timer/Counter 0 Compare Match B 1 1 0 Pin Change Interrupt 0 Request 1 1 1 Timer/Counter 0 Capture Event 14.12.
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ATtiny4/5/9/10 15. Programming interface 15.
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ATtiny4/5/9/10 The TPI is accessed via three pins, as follows: RESET: TPICLK: TPIDATA: Tiny Programming Interface enable input Tiny Programming Interface clock input Tiny Programming Interface data input/output In addition, the VCC and GND pins must be connected between the external programmer and the device. See Figure 15-2. Figure 15-2.
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ATtiny4/5/9/10 15.3.2 Disabling Provided that the NVM enable bit has been cleared, the TPI is automatically disabled if the RESET pin is released to inactive high state or, alternatively, if VHV is no longer applied to the RESET pin. If the NVM enable bit is not cleared a power down is required to exit TPI programming mode. See NVMEN bit in “TPISR – Tiny Programming Interface Status Register” on page 114. 15.3.3 Frame Format The TPI physical layer supports a fixed frame format.
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ATtiny4/5/9/10 15.3.6 Operation The TPI physical layer operates synchronously on the TPICLK provided by the external programmer. The dependency between the clock edges and data sampling or data change is shown in Figure 15-6. Data is changed at falling edges and sampled at rising edges. Figure 15-6. Data changing and Data sampling. TPICLK TPIDATA SAMPLE SETUP The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the layer is in Receive mode, waiting for a start bit.
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ATtiny4/5/9/10 The TPIDATA line is driven by a tri-state, push-pull driver with internal pull-up. The output driver is always enabled when a logical zero is sent. When sending successive logical ones, the output is only driven actively during the first clock cycle. After this, the output driver is automatically tri-stated and the TPIDATA line is kept high by the internal pull-up. The output is re-enabled, when the next logical zero is sent.
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ATtiny4/5/9/10 • Write messages. A write message is a request to write data. The write message is sent entirely by the external programmer. This message type is used with the SSTCS, SST, STPR, SOUT and SKEY instructions. • Read messages. A read message is a request to read data. The TPI reacts to the request by sending the byte operands. This message type is used with the SLDCS, SLD and SIN instructions.
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ATtiny4/5/9/10 Table 15-1. Instruction Set Summary (Continued) Mnemonic Operand Description Operation SLDCS data, a Serial LoaD from Control and Status space using direct addressing data  CSS[a] SSTCS a, data Serial STore to Control and Status space using direct addressing CSS[a]  data SKEY Key, {8{data}} Serial KEY Key  {8{data}} 15.5.
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ATtiny4/5/9/10 15.5.4 SIN - Serial IN from i/o space using direct addressing The SIN instruction loads data byte from the I/O space to the shift register of the physical layer for serial read-out. The instuction uses direct addressing, the address consisting of the 6 address bits of the instruction, as shown in Table 15-5. Table 15-5. The Serial IN from i/o space (SIN) Instruction Operation Opcode Remarks data I/O[a] 0aa1 aaaa Bits marked ‘a’ form the direct, 6-bit addres 15.5.
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ATtiny4/5/9/10 15.5.8 SKEY - Serial KEY signaling The SKEY instruction is used to signal the activation key that enables NVM programming. The SKEY instruction is followed by the 8 data bytes that includes the activation key, as shown in Table 15-9. Table 15-9. The Serial KEY signaling (SKEY) Instruction Operation Opcode Remarks Key {8[data}} 1110 0000 Data bytes follow after instruction 15.6 Accessing the Non-Volatile Memory Controller By default, NVM programming is not enabled.
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ATtiny4/5/9/10 15.7.1 TPIIR – Tiny Programming Interface Identification Register Bit 7 6 5 CSS: 0x0F 4 3 2 1 0 Programming Interface Identification Code TPIIR Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bits 7:0 – TPIIC: Tiny Programming Interface Identification Code These bits give the identification code for the Tiny Programming Interface. The code can be used be the external programmer to identify the TPI.
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ATtiny4/5/9/10 15.7.3 TPISR – Tiny Programming Interface Status Register Bit 7 6 5 4 3 2 1 CSS: 0x00 – – – – – – NVMEN 0 – Read/Write R R R R R R R/W R Initial Value 0 0 0 0 0 0 0 0 TPIPCR • Bits 7:2, 0 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 1 – NVMEN: Non-Volatile Memory Programming Enabled NVM programming is enabled when this bit is set.
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ATtiny4/5/9/10 16. Memory Programming 16.
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ATtiny4/5/9/10 16.3.1 Non-Volatile Memory Lock Bits The ATtiny4/5/9/10 provide two Lock Bits, as shown in Table 16-1. Table 16-1.
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ATtiny4/5/9/10 Notes: 1. This section is read-only. Table 16-4. Number of Words and Pages in the Flash (ATtiny4/5) Section Size (Bytes) Page Size (Words) Pages WADDR PADDR 512 8 32 [3:1] [9:4] 8 8 1 [3:1] – 16 8 2 [3:1] [4:4] 8 8 1 [3:1] – Code (program memory) Configuration Signature (1) Calibration (1) Notes: 1. This section is read-only. 16.3.3 Configuration Section ATtiny4/5/9/10 have one configuration byte, which resides in the configuration section. See Table 16-5.
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ATtiny4/5/9/10 16.3.4 Signature Section The signature section is a dedicated memory area used for storing miscellaneous device information, such as the device signature. Most of this memory section is reserved for internal use, as shown in Table 16-7. Table 16-7. Signature bytes Signature word data Signature word address High byte Low byte 0x00 Device ID 1 Manufacturer ID 0x01 Reserved for internal use Device ID 2 0x02 ...
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ATtiny4/5/9/10 When the NVM Controller is busy performing an operation it will signal this via the NVM Busy Flag in the NVM Control and Status Register. See “NVMCSR - Non-Volatile Memory Control and Status Register” on page 123. The NVM Command Register is blocked for write access as long as the busy flag is active. This is to ensure that the current command is fully executed before a new command can start.
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ATtiny4/5/9/10 16.4.3 Programming the Flash The Flash can be written word-by-word. Before writing a Flash word, the Flash target location must be erased. Writing to an un-erased Flash word will corrupt its content. The Flash is word-accessed for writing, and the data space uses byte-addressing to access Flash that has been mapped to data memory. It is therefore important to write the word in the correct order to the Flash, namely low bytes before high bytes.
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ATtiny4/5/9/10 1. Write the SECTION_ERASE command to the NVMCMD register 2. Start the erase operation by writing a dummy byte to the high byte of any word location inside the configuration section 3. Wait until the NVMBSY bit has been cleared 16.4.3.5 Writing a Configuration Word The algorithm for writing a Configuration word is as follows. 1. Write the WORD_WRITE command to the NVMCMD register 2. Write the low byte of the data to the low byte of a configuration word location 3.
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ATtiny4/5/9/10 16.6.2 Exiting External Programming Mode Clear the NVM enable bit to disable NVM programming, then release the RESET pin. See NVMEN bit in “TPISR – Tiny Programming Interface Status Register” on page 114.  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 16.7 Register Description 16.7.1 NVMCSR - Non-Volatile Memory Control and Status Register Bit 7 6 5 4 3 2 1 NVMBSY – – – – – – – Read/Write R/W R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0x32 0 NVMCSR • Bit 7 - NVMBSY: Non-Volatile Memory Busy This bit indicates the NVM memory (Flash memory and Lock Bits) is busy, being programmed. This bit is set when a program operation is started, and it remains set until the operation has been completed.
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ATtiny4/5/9/10 17. Electrical Characteristics 17.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground................................ -0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.
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ATtiny4/5/9/10 Table 17-1. Symbol DC Characteristics. TA = -40C to +85C (Continued) Parameter Condition Power Supply Current(6) ICC Power-down mode(7) Notes: Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.2 0.5 mA Active 4MHz, VCC = 3V 0.8 1.2 mA Active 8MHz, VCC = 5V 2.7 4 mA Idle 1MHz, VCC = 2V 0.02 0.2 mA Idle 4MHz, VCC = 3V 0.13 0.5 mA Idle 8MHz, VCC = 5V 0.6 1.5 mA WDT enabled, VCC = 3V 4.5 10 A WDT disabled, VCC = 3V 0.15 2 A 1.
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ATtiny4/5/9/10 17.4 Clock Characteristics 17.4.1 Accuracy of Calibrated Internal Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 18-39 on page 150 and Figure 18-40 on page 150. Table 17-2.
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ATtiny4/5/9/10 17.5 System and Reset Characteristics Table 17-4. Symbol Reset, VLM, and Internal Voltage Characteristics Parameter VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin tTOUT Note: Condition Typ(1) 0.2 VCC VCC = 1.8V VCC = 3V VCC = 5V Time-out after reset Max(1) Units 0.9VCC V 2000 700 400 32 ns 64 128 ms 1. Values are guidelines, only 17.5.1 Power-On Reset Table 17-5. Symbol Characteristics of Enhanced Power-On Reset.
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ATtiny4/5/9/10 17.6 Analog Comparator Characteristics Table 17-7. Analog Comparator Characteristics, TA = -40C - 85C Symbol Parameter Condition VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.8V - 5.5 1 tAPD tDPD 17.
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ATtiny4/5/9/10 17.8 Serial Programming Characteristics Figure 17-3. Serial Programming Timing Receive Mode Transmit Mode TPIDATA tIVCH tCHIX tCLOV TPICLK tCLCH tCHCL tCLCL Table 17-9.
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ATtiny4/5/9/10 18. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
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ATtiny4/5/9/10 18.2 Active Supply Current Figure 18-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0.7 5.5 V 0.6 5.0 V 0.5 4.5 V ICC (mA) 4.0 V 0.4 3.3 V 0.3 2.7 V 0.2 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 18-2. Active Supply Current vs. frequency (1 - 12 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 5 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC (mA) 3 2.5 4.0 V 2 1.5 3.
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ATtiny4/5/9/10 Figure 18-3. Active Supply Current vs. VCC (Internal Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 8 MHz 3.5 -40 °C 25 °C 85 °C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 18-4. Active Supply Current vs. VCC (Internal Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 1 MHz 1 0.9 -40 °C 25 °C 85 °C 0.8 0.7 ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATtiny4/5/9/10 Figure 18-5. Active Supply Current vs. VCC (Internal Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 128 KHz 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 18-6. Active Supply Current vs. VCC (External Clock, 32 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 32 KHz 0.04 -40 °C 85 °C 25 °C 0.035 0.03 ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATtiny4/5/9/10 18.3 Idle Supply Current Figure 18-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0,1 0,09 5.5 V ICC (mA) 0,08 0,07 5.0 V 0,06 4.5 V 0,05 4.0 V 0,04 3.3 V 0,03 2.7 V 0,02 1.8 V 0,01 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 18-8. Idle Supply Current vs. Frequency (1 - 12 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 1 5.5 V 5.0 V 0,8 4.5 V ICC (mA) 0,6 4.0 V 0,4 3.
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ATtiny4/5/9/10 Figure 18-9. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 0,7 85 °C 25 °C -40 °C 0,6 ICC (mA) 0,5 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 18-10. Idle Supply Current vs. VCC (Internal Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs.
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ATtiny4/5/9/10 18.4 Power-down Supply Current Figure 18-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 0.5 85 °C 0.45 0.4 0.35 ICC (uA) 0.3 0.25 0.2 0.15 25 °C 0.1 -40 °C 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 18-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs.
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ATtiny4/5/9/10 18.5 Pin Pull-up Figure 18-13. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 60 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) Figure 18-14. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs.
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ATtiny4/5/9/10 Figure 18-15. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 160 140 120 IOP (uA) 100 80 60 40 20 25 °C 85 °C -40 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 18-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs.
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ATtiny4/5/9/10 Figure 18-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 60 50 IRESET (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0,5 1 1,5 2,5 2 3 VRESET (V) Figure 18-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
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ATtiny4/5/9/10 18.6 Pin Driver Strength Figure 18-19. I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 1.8V 0.8 0.7 85 °C 0.6 VOL (V) 0.5 25 °C 0.4 -40 °C 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOL (mA) Figure 18-20. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0.8 0.7 85 °C 0.6 VOL (V) 0.5 25 °C -40 °C 0.4 0.3 0.2 0.
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ATtiny4/5/9/10 Figure 18-21. I/O pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 1 85 °C 0.8 -40 °C 25 °C VOL (V) 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 18-22. I/O Pin Output Voltage vs. Source Current (VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 1.8V 2 1.8 1.6 VOH (V) 1.4 1.2 -40 °C 1 25 °C 0.8 85 °C 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
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ATtiny4/5/9/10 Figure 18-23. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.1 2.9 VOH (V) 2.7 2.5 -40 °C 25 °C 2.3 85 °C 2.1 1.9 1.7 1.5 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 18-24. I/O Pin output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5.2 5 VOH (V) 4.8 4.6 4.4 -40 °C 25 °C 4.2 85 °C 4 0 2 4 6 8 10 12 14 16 18 20 IOH (mA)  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 Figure 18-25. Reset Pin as I/O, Output Voltage vs. Sink Current OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O 1 3.0 V 1.8 V 0.9 0.8 0.7 5.0 V VOL (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 IOL (mA) Figure 18-26. Reset Pin as I/O, Output Voltage vs. Source Current OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O 5 4 VOH (V) 3 5.0 V 2 1 3.0 V 1.8 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOH (mA)  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 18.7 Pin Threshold and Hysteresis Figure 18-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, I/O PIN READ AS '1' 3,5 85 °C 25 °C -40 °C 3 Threshold (V) 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 18-28. I/O Pin Input threshold Voltage vs. VCC (VIL, I/O Pin Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs.
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ATtiny4/5/9/10 Figure 18-29. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 1 0,9 0,8 Input Hysteresis (V) 0,7 0,6 -40 °C 0,5 25 °C 0,4 85 °C 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 18-30. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) RESET PIN AS I/O THRESHOLD VOLTAGE vs.
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ATtiny4/5/9/10 Figure 18-31. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIL, RESET READ AS '0' 2,5 85 °C 25 °C -40 °C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 4,5 5 5,5 VCC (V) Figure 18-32. Reset Input Hysteresis vs. VCC (Reset Pin Used as I/O) RESET PIN AS I/O, INPUT HYSTERESIS vs.
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ATtiny4/5/9/10 Figure 18-33. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, I/O PIN READ AS '1' 2,5 Threshold (V) 2 1,5 -40 °C 25 °C 1 85 °C 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 18-34. Reset Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs.
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ATtiny4/5/9/10 Figure 18-35. Reset Pin, Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 1 Input Hysteresis (V) 0,8 0,6 -40 °C 0,4 25 °C 85 °C 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 18.8 Analog Comparator Offset Figure 18-36. Analog Comparator Offset ANALOG COMPARATOR OFFSET VCC = 5V 0.006 -40 Offset 0.004 25 0.002 85 0 0 1 2 3 4 5 VIN  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 18.9 Internal Oscillator Speed Figure 18-37. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 110 109 108 Frequency (kHz) 107 -40 °C 106 105 25 °C 104 103 102 101 85 °C 100 99 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 18-38. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 110 109 108 Frequency (kHz) 107 106 105 104 1.8 V 103 2.7 V 102 3.3 V 101 4.0 V 5.
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ATtiny4/5/9/10 Figure 18-39. Calibrated Oscillator Frequency vs. VCC CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 8.4 -40 °C 8.2 Frequency (MHz) 25 °C 85 °C 8 7.8 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 18-40. Calibrated Oscillator Frequency vs. Temperature CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. TEMPERATURE 8.3 8.2 Frequency (MHz) 8.1 8 7.9 5.0 V 7.8 3.0 V 7.7 1.8 V 7.6 -40 -20 0 20 40 60 80 100 Temperature  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 Figure 18-41. Calibrated Oscillator Frequency vs, OSCCAL Value CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE VCC = 3V 16 25 °C 85 °C -40 °C 14 Frequency (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 18.10 VLM Thresholds Figure 18-42. VLM1L Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 001 1.42 1.41 Threshold (V) 1.4 1.39 1.38 1.37 1.36 1.35 1.
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ATtiny4/5/9/10 Figure 18-43. VLM1H Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 010 1.7 Threshold (V) 1.65 1.6 1.55 1.5 1.45 1.4 -40 -20 0 20 40 60 80 100 60 80 100 Temperature (C) Figure 18-44. VLM2 Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 011 2.48 Threshold (V) 2.47 2.46 2.45 2.44 2.43 -40 -20 0 20 40 Temperature (C)  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 Figure 18-45. VLM3 Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 100 3.9 Threshold (V) 3.8 3.7 3.6 3.5 3.4 -40 -20 0 20 40 60 80 100 Temperature (C) 18.11 Current Consumption of Peripheral Units Figure 18-46. ADC Current vs. VCC (ATtiny5/10, only) ADC CURRENT vs. VCC 4.0 MHz FREQUENCY 700 600 ICC (uA) 500 400 300 200 100 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 Figure 18-47. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 140 120 ICC (uA) 100 25 ˚C 80 60 40 20 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 18-48. VCC Level Monitor Current vs. VCC VLM SUPPLY CURRENT vs. VCC 0.35 0.3 VLM2:0 = 001 VLM2:0 = 010 VLM2:0 = 011 0.25 ICC (mA) VLM2:0 = 100 0.2 0.15 0.1 0.05 0 VLM2:0 = 000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 Figure 18-49. Temperature Dependence of VLM Current vs. VCC VLM SUPPLY CURRENT vs. VCC VLM2:0 = 001 350 -40 °C 300 25 °C 85 °C ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 18-50. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 9 -40 °C 25 °C 85 °C 8 7 ICC (uA) 6 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V)  2018 Microchip Technology Inc.
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ATtiny4/5/9/10 18.12 Current Consumption in Reset and Reset Pulsewidth Figure 18-51. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 0,5 0,4 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V ICC (mA) 0,3 0,2 1.8 V 0,1 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Note: The default clock source for the device is always the internal 8 MHz oscillator.
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ATtiny4/5/9/10 19.
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ATtiny4/5/9/10 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
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ATtiny4/5/9/10 20.
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ATtiny4/5/9/10 Mnemonics Operands Description Operation Flags #Clocks SBI A, b Set Bit in I/O Register I/O(A, b)  1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b)  0 None 1 BST Rr, b Bit Store from Register to T T  Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b)  T None 1 SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SE
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ATtiny4/5/9/10 21. Packaging Information 21.1 6ST1 D 5 6 E E1 A 4 A2 Pin #1 ID b A1 3 2 0.10 C SEATING PLANE A 1 A C Side View e Top View A2 A 0.10 C SEATING PLANE c 0.25 A1 O C C View A-A SEATING PLANE SEE VIEW B L View B COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package is compliant with JEDEC specification MO-178 Variation AB 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrustion or gate burrs shall not exceed 0.
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ATtiny4/5/9/10 21.2 8MA4 [ F F F 6,'( 9,(: ( 3LQ ,' ' $ $ 723 9,(: ' H &20021 ',0(16,216 8QLW RI 0HDVXUH PP , ( 6<0%2/ 0,1 120 0$; $ ± ± $ - C 1RWH $// ',0(16,216 $5( ,1 PP $1*/(6 ,1 '(*5((6 $ 01-"/"3*5: "11-*&4 50 5)& &9104&% 1"% "4 8&-- "4 5)& 5&3.*/"-4 $01-"/"3*5: 4)"-- /05 &9$&&% NN 8"31"(& 4)"-- /05 &9$&&% NN 3&'&3 +&%&$ .0 .
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ATtiny4/5/9/10 22. Errata The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device. 22.1 ATtiny4 22.1.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.1.2 Rev. D • ESD HBM (ESD STM 5.
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ATtiny4/5/9/10 22.2 ATtiny5 22.2.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.2.2 Rev. D • ESD HBM (ESD STM 5.1) level 1000V • Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.
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ATtiny4/5/9/10 22.3 ATtiny9 22.3.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.3.2 Rev. D • ESD HBM (ESD STM 5.1) level 1000V • Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.
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ATtiny4/5/9/10 22.4 ATtiny10 22.4.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.4.2 Rev. C – D • ESD HBM (ESD STM 5.1) level 1000V • Programming Lock Bits 1. ESD HBM (ESD STM 5.
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ATtiny4/5/9/10 23. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 23.1 Rev. A – 08/2018 1. • Updated the document to Microchip style • New Microchip document number. Previous version was Atmel document 8127 rev. H 2. • Updated “Ordering Information” on page 9 • Reverse back to the Ordering codes prior to Rev.
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ATtiny4/5/9/10 23.4 1. 23.5 Rev. 8127F – 02/2013 • Updated “Ordering Information” on page 9 Rev. 8127E – 11/11 1. Updated: – Data sheet status changed from Preliminary to Final – Ordering information on page 161, page 162, page 163, and page 164 23.6 Rev. 8127D – 02/10 1. Added UDFN package in “Features” on page 1, “Pin Configurations” on page 8, “Ordering Information” on page 161, and in “Packaging Information” on page 161 2. Updated Figure 9-2 and Figure 9-3 in Section 9.2.
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ATtiny4/5/9/10 – “Alternate Functions of Port B” on page 58 – “Overview” on page 91 – “Physical Layer of Tiny Programming Interface” on page 104 – “Overview” on page 115 – “ADC Characteristics (ATtiny5/10, only)” on page 128 – “Supply Current of I/O Modules” on page 130 – “Register Summary” on page 157 – “Ordering Information” on page 161 5. Added figure: – “Using an External Programmer for In-System Programming via TPI” on page 105 6. Updated figure: – “Data Memory Map (Byte Addressing)” on page 25 7.
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ATtiny4/5/9/10 The Microchip Web Site Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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ATtiny4/5/9/10 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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ATtiny4/5/9/10 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.