Datasheet

41.8.7 SPI Interrupt Disable Register
Name: SPI_IDR
Offset: 0x18
Reset: –
Property: Write-only
This register can only be written if the WPITEN bit is cleared in the SPI Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Disables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
UNDES TXEMPTY NSSR
Access
W W W
Reset – – –
Bit 7 6 5 4 3 2 1 0
OVRES MODF TDRE RDRF
Access
W W W W
Reset – – – –
Bit 10 – UNDES Underrun Error Interrupt Disable
Bit 9 – TXEMPTY
Transmission Registers Empty Disable
Bit 8 – NSSR NSS Rising Interrupt Disable
Bit 3 – OVRES Overrun Error Interrupt Disable
Bit 2 – MODF Mode Fault Error Interrupt Disable
Bit 1 – TDRE SPI Transmit Data Register Empty Interrupt Disable
Bit 0 – RDRF Receive Data Register Full Interrupt Disable
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
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echnology Inc.
Datasheet
DS60001527D-page 999