Datasheet

Bit 3 – OVRES Overrun Error Status (cleared on read)
An overrun occurs when SPI_RDR is loaded at least twice from the internal shift register since the last read of
SPI_RDR.
Value Description
0
No overrun has been detected since the last read of SPI_SR.
1
An overrun has occurred since the last read of SPI_SR.
Bit 2 – MODF Mode Fault Error (cleared on read)
Value Description
0
No mode fault has been detected since the last read of SPI_SR.
1
A mode fault occurred since the last read of SPI_SR.
Bit 1 – TDRE T
ransmit Data Register Empty (cleared by writing SPI_TDR)
0: Data has been written to SPI_TDR and not yet transferred to the internal shift register.
1: The last data written in SPI_TDR has been transferred to the internal shift register.
TDRE is cleared when the SPI is disabled or at reset. Enabling the SPI sets the TDRE flag.
Bit 0 – RDRF Receive Data Register Full (cleared by reading SPI_RDR)
0: No data has been received since the last read of SPI_RDR.
1: Data has been received and the received data has been transferred from the internal shift register to SPI_RDR
since the last read of SPI_RDR.
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 997